Remove comments that are obsolete since r6028.

[coreboot.git] / src / mainboard / iwill / dk8s2 / romstage.c

diff --git a/src/mainboard/iwill/dk8s2/romstage.c b/src/mainboard/iwill/dk8s2/romstage.c
index ea4eefafb43acfdfa49eeee84f434667b8d74958..5c9d8251d69ea929ab561eba2dac36f9611ae799 100644 (file)
--- a/src/mainboard/iwill/dk8s2/romstage.c
+++ b/src/mainboard/iwill/dk8s2/romstage.c
@@ -1,10 +1,4 @@
-#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
-
-#define SET_NB_CFG_54 1 
-
-//used by raminit
-#define QRANK_DIMM_SUPPORT 1
+#define SET_NB_CFG_54 1
 
 //used by incoherent_ht
 //#define K8_ALLOCATE_IO_RANGE 1
@@ -26,11 +20,9 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
 
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
@@ -44,7 +36,7 @@
 #include "lib/delay.c"
 
 #include "northbridge/amd/amdk8/debug.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 
 #include "northbridge/amd/amdk8/setup_resource_map.c"
@@ -90,14 +82,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 }
 
 #include "northbridge/amd/amdk8/amdk8.h"
-#include "northbridge/amd/amdk8/coherent_ht.c"
-
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-
+#include "northbridge/amd/amdk8/coherent_ht.c"
 #include "northbridge/amd/amdk8/raminit.c"
-
 #include "lib/generic_sdram.c"
-#include "lib/ramtest.c"
 
  /* tyan does not want the default */
 #include "northbridge/amd/amdk8/resourcemap.c"
@@ -113,7 +101,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #define DIMM6 0x56
 #define DIMM7 0x57
 
-#include "cpu/amd/car/copy_and_run.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 
 #include "cpu/amd/model_fxx/init_cpus.c"
@@ -126,20 +113,19 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
        static const uint16_t spd_addr[] = {
-                       //first node
+                       // first node
                         DIMM0, DIMM2, 0, 0,
                         DIMM1, DIMM3, 0, 0,
-#if CONFIG_MAX_PHYSICAL_CPUS > 1
-                       //second node
+
+                       // second node
                         DIMM4, DIMM6, 0, 0,
                         DIMM5, DIMM7, 0, 0,
-#endif
-
        };
 
-       struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+       struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+               + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 
-        int needs_reset; int i;
+        int needs_reset;
         unsigned bsp_apicid = 0;
 
         if (!cpu_init_detectedx && boot_cpu()) {
@@ -170,21 +156,21 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 
 #if CONFIG_MEM_TRAIN_SEQ == 1
-        set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram 
+        set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
 #endif
        setup_coherent_ht_domain(); // routing table and start other core0
 
        wait_all_core0_started();
 #if CONFIG_LOGICAL_CPUS==1
         // It is said that we should start core1 after all core0 launched
-       /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, 
+       /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
         * So here need to make sure last core0 is started, esp for two way system,
-        * (there may be apic id conflicts in that case) 
+        * (there may be apic id conflicts in that case)
         */
         start_other_cores();
        wait_all_other_cores_started(bsp_apicid);
 #endif
-       
+
        /* it will set up chains and store link pair for optimization later */
         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 
@@ -207,7 +193,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         {
                 msr_t msr;
                        msr=rdmsr(0xc0010042);
-                       print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); 
+                       print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 
         }
 #endif