#include <console/console.h>
#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
#define INT_D 3
#define PCI_IRQ(dev, intLine) (((dev)<<2) | intLine)
-
-static void xe7501devkit_register_buses(struct mp_config_table *mc)
-{
- // Bus ID, Bus Type
- smp_write_bus(mc, PCI_BUS_CHIPSET, BUSTYPE_PCI);
- smp_write_bus(mc, PCI_BUS_E7501_HI_B, BUSTYPE_PCI);
- smp_write_bus(mc, PCI_BUS_P64H2_2_B, BUSTYPE_PCI);
- smp_write_bus(mc, PCI_BUS_P64H2_2_A, BUSTYPE_PCI);
- smp_write_bus(mc, PCI_BUS_E7501_HI_D, BUSTYPE_PCI);
- smp_write_bus(mc, PCI_BUS_P64H2_1_B, BUSTYPE_PCI);
- smp_write_bus(mc, PCI_BUS_P64H2_1_A, BUSTYPE_PCI);
- smp_write_bus(mc, PCI_BUS_ICH3, BUSTYPE_PCI);
- smp_write_bus(mc, SUPERIO_BUS, BUSTYPE_ISA);
-}
+static int bus_isa;
static void xe7501devkit_register_ioapics(struct mp_config_table *mc)
{
// TODO: Gack. This is REALLY ugly.
// Southbridge IOAPIC
- smp_write_ioapic(mc, IOAPIC_ICH3, 0x20, 0xfec00000); // APIC ID, Version, Address
+ smp_write_ioapic(mc, IOAPIC_ICH3, 0x20, IO_APIC_ADDR); // APIC ID, Version, Address
// P64H2#2 Bus A IOAPIC
dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(30, 0));
if (!dev)
- BUG(); // Config.lb error?
+ BUG();
res = find_resource(dev, PCI_BASE_ADDRESS_0);
smp_write_ioapic(mc, IOAPIC_P64H2_2_BUS_A, P64H2_IOAPIC_VERSION, res->base);
// P64H2#2 Bus B IOAPIC
dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(28, 0));
if (!dev)
- BUG(); // Config.lb error?
+ BUG();
res = find_resource(dev, PCI_BASE_ADDRESS_0);
smp_write_ioapic(mc, IOAPIC_P64H2_2_BUS_B, P64H2_IOAPIC_VERSION, res->base);
// P64H2#1 Bus A IOAPIC
dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(30, 0));
if (!dev)
- BUG(); // Config.lb error?
+ BUG();
res = find_resource(dev, PCI_BASE_ADDRESS_0);
smp_write_ioapic(mc, IOAPIC_P64H2_1_BUS_A, P64H2_IOAPIC_VERSION, res->base);
// P64H2#1 Bus B IOAPIC
dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(28, 0));
if (!dev)
- BUG(); // Config.lb error?
+ BUG();
res = find_resource(dev, PCI_BASE_ADDRESS_0);
smp_write_ioapic(mc, IOAPIC_P64H2_1_BUS_B, P64H2_IOAPIC_VERSION, res->base);
}
{
// Chipset PCI bus
// Type Trigger | Polarity Bus ID IRQ APIC ID PIN#
- smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, PCI_BUS_CHIPSET, 0, MP_APIC_ALL, 0);
- smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, PCI_BUS_CHIPSET, 0, MP_APIC_ALL, 1);
+ mptable_lintsrc(mc, PCI_BUS_CHIPSET);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_CHIPSET, PCI_IRQ(29, INT_A), IOAPIC_ICH3, 16); // USB 1.1 Controller #1
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_CHIPSET, PCI_IRQ(31, INT_B), IOAPIC_ICH3, 17); // SMBus
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_CHIPSET, PCI_IRQ(29, INT_C), IOAPIC_ICH3, 18); // USB 1.1 Controller #3
// TODO: Not sure how to handle BT_INTR# signals from the P64H2s. Do we even need to, in APIC mode?
- // Super I/O (ISA interrupts)
- smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 0, IOAPIC_ICH3, 0);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 1, IOAPIC_ICH3, 1);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 0, IOAPIC_ICH3, 2);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 3, IOAPIC_ICH3, 3);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 4, IOAPIC_ICH3, 4);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 6, IOAPIC_ICH3, 6);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 8, IOAPIC_ICH3, 8);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 9, IOAPIC_ICH3, 9);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 12, IOAPIC_ICH3, 12);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 13, IOAPIC_ICH3, 13);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 14, IOAPIC_ICH3, 14);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 15, IOAPIC_ICH3, 15);
+ mptable_add_isa_interrupts(mc, bus_isa, IOAPIC_ICH3, 0);
}
static void *smp_write_config_table(void* v)
{
- static const char sig[4] = MPC_SIGNATURE;
- static const char oem[8] = "COREBOOT";
- static const char productid[12] = "XE7501DEVKIT";
- struct mp_config_table *mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
- memset(mc, 0, sizeof(*mc));
+ struct mp_config_table *mc;
- memcpy(mc->mpc_signature, sig, sizeof(sig));
- memcpy(mc->mpc_oem, oem, sizeof(oem));
- memcpy(mc->mpc_productid, productid, sizeof(productid));
+ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
- mc->mpc_length = sizeof(*mc); // initially just the header
- mc->mpc_spec = 0x04; // Multiprocessing Spec V1.4
- mc->mpc_lapic = LAPIC_ADDR;
+ mptable_init(mc, LAPIC_ADDR);
smp_write_processors(mc);
- xe7501devkit_register_buses(mc);
+ mptable_write_buses(mc, NULL, &bus_isa);
xe7501devkit_register_ioapics(mc);
xe7501devkit_register_interrupts(mc);
unsigned long write_smp_table(unsigned long addr)
{
void *v;
- v = smp_write_floating_table(addr);
+ v = smp_write_floating_table(addr, 0);
return (unsigned long)smp_write_config_table(v);
}
projects / coreboot.git / blobdiff