-/*\r
- * Ported to Intel XE7501DEVKIT from Island Aruma\r
- * written by Stefan Reinauer <stepan@openbios.org>\r
- * (C) 2005 Stefan Reinauer\r
- * (C) 2005 Digital Design Corporation\r
- */\r
-\r
-#include <console/console.h>\r
-#include <string.h>\r
-#include <arch/acpi.h>\r
-#include <device/pci.h>\r
-#include <device/pci_ids.h>\r
-#include <assert.h>\r
-#include "bus.h"\r
-#include "ioapic.h"\r
-\r
-unsigned long acpi_dump_apics(unsigned long current)\r
-{\r
- unsigned int irq_start = 0;\r
- device_t dev = 0;\r
- struct resource* res = NULL;\r
-\r
- \r
- // SJM: Hard-code CPU LAPIC entries for now\r
- // Use SourcePoint numbering of processors\r
- current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 6);\r
- current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 7);\r
- current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 2, 0);\r
- current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 3, 1);\r
- \r
-\r
- // Southbridge IOAPIC\r
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_ICH3, 0xfec00000, irq_start);\r
- irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;\r
-\r
- // P64H2#2 Bus A IOAPIC\r
- dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(30, 0)); \r
- if (!dev)\r
- BUG(); // Config.lb error?\r
- res = find_resource(dev, PCI_BASE_ADDRESS_0);\r
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_2_BUS_A, res->base, irq_start);\r
- irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;\r
-\r
- // P64H2#2 Bus B IOAPIC\r
- dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(28, 0)); \r
- if (!dev)\r
- BUG(); // Config.lb error?\r
- res = find_resource(dev, PCI_BASE_ADDRESS_0);\r
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_2_BUS_B, res->base, irq_start);\r
- irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;\r
-\r
-\r
- // P64H2#1 Bus A IOAPIC\r
- dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(30, 0)); \r
- if (!dev)\r
- BUG(); // Config.lb error?\r
- res = find_resource(dev, PCI_BASE_ADDRESS_0);\r
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_1_BUS_A, res->base, irq_start);\r
- irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;\r
-\r
- // P64H2#1 Bus B IOAPIC\r
- dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(28, 0)); \r
- if (!dev)\r
- BUG(); // Config.lb error?\r
- res = find_resource(dev, PCI_BASE_ADDRESS_0);\r
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_1_BUS_B, res->base, irq_start);\r
- irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;\r
-\r
- // Map ISA IRQ 0 to IRQ 2\r
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, 1, 0, 2, 0);\r
-\r
- // IRQ9 differs from ISA standard - ours is active high, level-triggered\r
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, 0, 9, 9, 0xD);\r
-\r
- return current;\r
-}\r
-\r
-\r
-unsigned long write_acpi_tables(unsigned long start)\r
-{\r
- unsigned long current;\r
- acpi_rsdp_t *rsdp;\r
- acpi_rsdt_t *rsdt;\r
- acpi_madt_t *madt;\r
-\r
- /* Align ACPI tables to 16byte */\r
- start = ( start + 0x0f ) & -0x10;\r
- current = start;\r
- \r
- printk_info("ACPI: Writing ACPI tables at %lx...\n", start);\r
-\r
- /* We need at least an RSDP and an RSDT Table */\r
- rsdp = (acpi_rsdp_t *) current;\r
- current += sizeof(acpi_rsdp_t);\r
- rsdt = (acpi_rsdt_t *) current;\r
- current += sizeof(acpi_rsdt_t);\r
-\r
- /* clear all table memory */\r
- memset((void *)start, 0, current - start);\r
- \r
- acpi_write_rsdp(rsdp, rsdt);\r
- acpi_write_rsdt(rsdt);\r
- \r
- /*\r
- * We explicitly add these tables later on:\r
- */\r
- /* QNX wants an MADT */\r
- printk_debug("ACPI: * MADT\n");\r
-\r
- madt = (acpi_madt_t *) current;\r
- acpi_create_madt(madt);\r
- current+=madt->header.length;\r
- acpi_add_table(rsdt,madt);\r
-\r
- printk_info("ACPI: done.\n");\r
- return current;\r
-}\r
-\r
+/*
+ * Ported to Intel XE7501DEVKIT from Agami Aruma
+ * written by Stefan Reinauer <stepan@openbios.org>
+ * (C) 2005 Stefan Reinauer
+ * (C) 2005 Digital Design Corporation
+ */
+
+#include <console/console.h>
+#include <string.h>
+#include <arch/acpi.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <assert.h>
+#include "bus.h"
+#include "ioapic.h"
+
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+ /* Just a dummy */
+ return current;
+}
+
+unsigned long acpi_fill_slit(unsigned long current)
+{
+ // Not implemented
+ return current;
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+ // Not implemented
+ return current;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ unsigned int irq_start = 0;
+ device_t dev = 0;
+ struct resource* res = NULL;
+
+
+ // SJM: Hard-code CPU LAPIC entries for now
+ // Use SourcePoint numbering of processors
+ current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 6);
+ current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 7);
+ current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 2, 0);
+ current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 3, 1);
+
+
+ // Southbridge IOAPIC
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_ICH3, 0xfec00000, irq_start);
+ irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
+
+ // P64H2#2 Bus A IOAPIC
+ dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(30, 0));
+ if (!dev)
+ BUG(); // Config.lb error?
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_2_BUS_A, res->base, irq_start);
+ irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
+
+ // P64H2#2 Bus B IOAPIC
+ dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(28, 0));
+ if (!dev)
+ BUG(); // Config.lb error?
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_2_BUS_B, res->base, irq_start);
+ irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
+
+
+ // P64H2#1 Bus A IOAPIC
+ dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(30, 0));
+ if (!dev)
+ BUG(); // Config.lb error?
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_1_BUS_A, res->base, irq_start);
+ irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
+
+ // P64H2#1 Bus B IOAPIC
+ dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(28, 0));
+ if (!dev)
+ BUG(); // Config.lb error?
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_1_BUS_B, res->base, irq_start);
+ irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
+
+ // Map ISA IRQ 0 to IRQ 2
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, 1, 0, 2, 0);
+
+ // IRQ9 differs from ISA standard - ours is active high, level-triggered
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, 0, 9, 9, 0xD);
+
+ return current;
+}
+
+
+unsigned long write_acpi_tables(unsigned long start)
+{
+ unsigned long current;
+ acpi_rsdp_t *rsdp;
+ acpi_rsdt_t *rsdt;
+ acpi_madt_t *madt;
+
+ /* Align ACPI tables to 16byte */
+ start = ( start + 0x0f ) & -0x10;
+ current = start;
+
+ printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
+
+ /* We need at least an RSDP and an RSDT Table */
+ rsdp = (acpi_rsdp_t *) current;
+ current += sizeof(acpi_rsdp_t);
+ rsdt = (acpi_rsdt_t *) current;
+ current += sizeof(acpi_rsdt_t);
+
+ /* clear all table memory */
+ memset((void *)start, 0, current - start);
+
+ acpi_write_rsdp(rsdp, rsdt, NULL);
+ acpi_write_rsdt(rsdt);
+
+ /*
+ * We explicitly add these tables later on:
+ */
+ /* QNX wants an MADT */
+ printk(BIOS_DEBUG, "ACPI: * MADT\n");
+
+ madt = (acpi_madt_t *) current;
+ acpi_create_madt(madt);
+ current+=madt->header.length;
+ acpi_add_table(rsdp,madt);
+
+ printk(BIOS_INFO, "ACPI: done.\n");
+ return current;
+}
+
projects / coreboot.git / blobdiff