-uses HAVE_MP_TABLE\r
-uses HAVE_ACPI_TABLES\r
-uses HAVE_PIRQ_TABLE\r
-uses HAVE_FALLBACK_BOOT\r
-uses HAVE_OPTION_TABLE\r
-uses IRQ_SLOT_COUNT\r
-uses CONFIG_MAX_CPUS\r
-uses CONFIG_LOGICAL_CPUS\r
-uses CONFIG_MAX_PHYSICAL_CPUS\r
-uses CONFIG_IOAPIC\r
-uses CONFIG_SMP\r
-uses CONFIG_ROM_STREAM\r
-uses STACK_SIZE\r
-uses HEAP_SIZE\r
-uses USE_OPTION_TABLE\r
-uses LB_CKS_RANGE_START\r
-uses LB_CKS_RANGE_END\r
-uses LB_CKS_LOC\r
-uses MAINBOARD_PART_NUMBER\r
-uses MAINBOARD_VENDOR\r
-uses MAINBOARD\r
-uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID\r
-uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID\r
-uses _RAMBASE\r
-uses TTYS0_BAUD\r
-uses TTYS0_BASE\r
-uses TTYS0_LCS\r
-uses DEFAULT_CONSOLE_LOGLEVEL\r
-uses MAXIMUM_CONSOLE_LOGLEVEL\r
-uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL\r
-uses CONFIG_CONSOLE_SERIAL8250\r
-uses CONFIG_UDELAY_TSC\r
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2\r
-uses HAVE_INIT_TIMER\r
-uses CONFIG_GDB_STUB\r
-uses CROSS_COMPILE\r
-uses CC\r
-uses HOSTCC\r
-uses OBJCOPY\r
-uses CONFIG_CHIP_NAME\r
-uses CONFIG_CONSOLE_VGA\r
-uses CONFIG_PCI_ROM_RUN\r
-uses DEBUG\r
-uses CPU_OPT\r
-uses CONFIG_IDE\r
-\r
-## The default definitions are used for these\r
-uses CONFIG_ROM_STREAM_START\r
-uses PAYLOAD_SIZE\r
-\r
-## These are defined in target Config.lb, don't add here\r
-uses USE_FALLBACK_IMAGE\r
-uses ROM_SIZE\r
-uses ROM_IMAGE_SIZE\r
-uses FALLBACK_SIZE\r
-uses LINUXBIOS_EXTRA_VERSION\r
-\r
-## These are defined in mainboard Config.lb, don't add here\r
-uses ROM_SECTION_SIZE\r
-uses ROM_SECTION_OFFSET\r
-uses _ROMBASE\r
-uses XIP_ROM_SIZE\r
-uses XIP_ROM_BASE\r
-\r
-###\r
-### Build options\r
-###\r
-\r
-##\r
-## Build code for the fallback boot?\r
-##\r
-default HAVE_FALLBACK_BOOT=0\r
-\r
-\r
-## Delay timer options\r
-##\r
-default CONFIG_UDELAY_TSC=1\r
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1\r
-\r
-##\r
-## Build code to export a programmable irq routing table\r
-##\r
-default HAVE_PIRQ_TABLE=1\r
-default IRQ_SLOT_COUNT=12\r
-\r
-##\r
-## Build code to export an x86 MP table\r
-## Useful for specifying IRQ routing values\r
-##\r
-default HAVE_MP_TABLE=1\r
-\r
-## Build code to export ACPI tables?\r
-default HAVE_ACPI_TABLES=1\r
-\r
-##\r
-## Build code to export a CMOS option table?\r
-##\r
-default HAVE_OPTION_TABLE=0\r
-\r
-## CMOS checksum definitions (units == bytes)\r
-## These must match the checksum record in cmos.layout\r
-default LB_CKS_RANGE_START=128\r
-default LB_CKS_RANGE_END=130\r
-default LB_CKS_LOC=131\r
-\r
-##\r
-## Build code for SMP support\r
-## Only worry about 2 micro processors\r
-## NOTE: CONFIG_MAX_CPUS is the number of LOGICAL CPUs,\r
-## so if CONFIG_LOGICAL_CPUS is 1, CONFIG_MAX_CPUS should be 4.\r
-##\r
-default CONFIG_SMP=1\r
-default CONFIG_MAX_CPUS=2\r
-default CONFIG_LOGICAL_CPUS=0\r
-default CONFIG_MAX_PHYSICAL_CPUS=2\r
-\r
-# VGA Console\r
-# NOTE: to initialize VGA, need to copy the VGA option ROM from the factory BIOS\r
-# to VGA.rom\r
-default CONFIG_CONSOLE_VGA=0\r
-default CONFIG_PCI_ROM_RUN=0\r
-\r
-##\r
-## Build code to setup a generic IOAPIC\r
-##\r
-default CONFIG_IOAPIC=1\r
-\r
-##\r
-## Motherboard identification\r
-##\r
-default MAINBOARD_PART_NUMBER="EIDXE7501DEVKIT"\r
-default MAINBOARD_VENDOR="Intel"\r
-default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086\r
-default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2480\r
-\r
-###\r
-### LinuxBIOS layout values\r
-###\r
-\r
-##\r
-## Use a small 8K stack\r
-##\r
-default STACK_SIZE=0x2000\r
-\r
-##\r
-## Use a small 16K heap\r
-##\r
-default HEAP_SIZE=0x4000\r
-\r
-##\r
-## CMOS settings not currently supported due to conflicts with factory BIOS\r
-##\r
-default USE_OPTION_TABLE = 0\r
-\r
-##\r
-## LinuxBIOS C code runs at this location in RAM\r
-##\r
-default _RAMBASE=0x00004000\r
-\r
-##\r
-## Load the payload from the ROM\r
-##\r
-default CONFIG_ROM_STREAM = 1\r
-\r
-###\r
-### Defaults of options that you may want to override in the target config file\r
-### \r
-\r
-##\r
-## The default compiler\r
-##\r
-default CC="$(CROSS_COMPILE)gcc -m32"\r
-default HOSTCC="gcc"\r
-\r
-##\r
-## Disable the gdb stub by default\r
-## \r
-default CONFIG_GDB_STUB=0\r
-\r
-##\r
-## The Serial Console\r
-##\r
-\r
-# To Enable the Serial Console\r
-default CONFIG_CONSOLE_SERIAL8250=1\r
-\r
-## Select the serial console baud rate\r
-default TTYS0_BAUD=115200\r
-#default TTYS0_BAUD=57600\r
-#default TTYS0_BAUD=38400\r
-#default TTYS0_BAUD=19200\r
-#default TTYS0_BAUD=9600\r
-#default TTYS0_BAUD=4800\r
-#default TTYS0_BAUD=2400\r
-#default TTYS0_BAUD=1200\r
-\r
-# Select the serial console base port\r
-default TTYS0_BASE=0x3f8\r
-\r
-# Select the serial protocol\r
-# This defaults to 8 data bits, 1 stop bit, and no parity\r
-default TTYS0_LCS=0x3\r
-\r
-##\r
-### Select the linuxBIOS loglevel\r
-##\r
-## EMERG 1 system is unusable \r
-## ALERT 2 action must be taken immediately \r
-## CRIT 3 critical conditions \r
-## ERR 4 error conditions \r
-## WARNING 5 warning conditions \r
-## NOTICE 6 normal but significant condition \r
-## INFO 7 informational \r
-## DEBUG 8 debug-level messages \r
-## SPEW 9 Way too many details \r
-\r
-## Request this level of debugging output\r
-default DEFAULT_CONSOLE_LOGLEVEL=8\r
-## At a maximum only compile in this level of debugging\r
-default MAXIMUM_CONSOLE_LOGLEVEL=8\r
-\r
-##\r
-## Select power on after power fail setting\r
-default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"\r
-\r
-## Things we may not have\r
-default CONFIG_IDE=1\r
-\r
-default DEBUG=1\r
-default CPU_OPT="-g"\r
-default CONFIG_CHIP_NAME=1\r
-\r
-### End Options.lb\r
-end\r
+uses HAVE_MP_TABLE
+uses CONFIG_ROMFS
+uses HAVE_ACPI_TABLES
+uses HAVE_ACPI_RESUME
+uses HAVE_PIRQ_TABLE
+uses HAVE_FALLBACK_BOOT
+uses HAVE_OPTION_TABLE
+uses IRQ_SLOT_COUNT
+uses CONFIG_MAX_CPUS
+uses CONFIG_LOGICAL_CPUS
+uses CONFIG_MAX_PHYSICAL_CPUS
+uses CONFIG_IOAPIC
+uses CONFIG_SMP
+uses CONFIG_ROM_PAYLOAD
+uses CONFIG_COMPRESSED_PAYLOAD_LZMA
+uses CONFIG_PRECOMPRESSED_PAYLOAD
+uses STACK_SIZE
+uses HEAP_SIZE
+uses USE_OPTION_TABLE
+uses LB_CKS_RANGE_START
+uses LB_CKS_RANGE_END
+uses LB_CKS_LOC
+uses MAINBOARD_PART_NUMBER
+uses MAINBOARD_VENDOR
+uses MAINBOARD
+uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+uses _RAMBASE
+uses TTYS0_BAUD
+uses TTYS0_BASE
+uses TTYS0_LCS
+uses DEFAULT_CONSOLE_LOGLEVEL
+uses MAXIMUM_CONSOLE_LOGLEVEL
+uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+uses CONFIG_CONSOLE_SERIAL8250
+uses CONFIG_UDELAY_TSC
+uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
+uses HAVE_INIT_TIMER
+uses CONFIG_GDB_STUB
+uses CROSS_COMPILE
+uses CC
+uses HOSTCC
+uses OBJCOPY
+uses CONFIG_CONSOLE_VGA
+uses CONFIG_PCI_ROM_RUN
+uses DEBUG
+#uses CPU_OPT
+uses CONFIG_IDE
+
+## The default definitions are used for these
+uses CONFIG_ROM_PAYLOAD_START
+uses PAYLOAD_SIZE
+
+## These are defined in target Config.lb, don't add here
+uses USE_FALLBACK_IMAGE
+uses ROM_SIZE
+uses ROM_IMAGE_SIZE
+uses FALLBACK_SIZE
+uses COREBOOT_EXTRA_VERSION
+
+## These are defined in mainboard Config.lb, don't add here
+uses ROM_SECTION_SIZE
+uses ROM_SECTION_OFFSET
+uses _ROMBASE
+uses XIP_ROM_SIZE
+uses XIP_ROM_BASE
+
+###
+### Build options
+###
+
+##
+## ROM_SIZE is the size of boot ROM that this board will use.
+##
+default ROM_SIZE=2097152
+default ROM_IMAGE_SIZE = 65536
+
+##
+## Build code for the fallback boot?
+##
+default HAVE_FALLBACK_BOOT=1
+default FALLBACK_SIZE=131072
+
+
+## Delay timer options
+##
+default CONFIG_UDELAY_TSC=1
+default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
+
+##
+## Build code to export a programmable irq routing table
+##
+default HAVE_PIRQ_TABLE=1
+default IRQ_SLOT_COUNT=12
+
+##
+## Build code to export an x86 MP table
+## Useful for specifying IRQ routing values
+##
+default HAVE_MP_TABLE=1
+
+## Build code to export ACPI tables?
+default HAVE_ACPI_TABLES=1
+
+##
+## Build code to export a CMOS option table?
+##
+default HAVE_OPTION_TABLE=0
+
+## CMOS checksum definitions (units == bytes)
+## These must match the checksum record in cmos.layout
+default LB_CKS_RANGE_START=128
+default LB_CKS_RANGE_END=130
+default LB_CKS_LOC=131
+
+##
+## Build code for SMP support
+## Only worry about 2 micro processors
+## NOTE: CONFIG_MAX_CPUS is the number of LOGICAL CPUs,
+## so if CONFIG_LOGICAL_CPUS is 1, CONFIG_MAX_CPUS should be 4.
+##
+default CONFIG_SMP=1
+default CONFIG_MAX_CPUS=2
+default CONFIG_LOGICAL_CPUS=0
+default CONFIG_MAX_PHYSICAL_CPUS=2
+
+# VGA Console
+# NOTE: to initialize VGA, need to copy the VGA option ROM from the factory BIOS
+# to VGA.rom
+default CONFIG_CONSOLE_VGA=0
+default CONFIG_PCI_ROM_RUN=0
+
+##
+## Build code to setup a generic IOAPIC
+##
+default CONFIG_IOAPIC=1
+
+##
+## Motherboard identification
+##
+default MAINBOARD_PART_NUMBER="EIDXE7501DEVKIT"
+default MAINBOARD_VENDOR="Intel"
+default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086
+default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2480
+
+###
+### coreboot layout values
+###
+
+##
+## Use a small 8K stack
+##
+default STACK_SIZE=0x2000
+
+##
+## Use a small 16K heap
+##
+default HEAP_SIZE=0x4000
+
+##
+## CMOS settings not currently supported due to conflicts with factory BIOS
+##
+default USE_OPTION_TABLE = 0
+
+##
+## Coreboot C code runs at this location in RAM
+##
+default _RAMBASE=0x00004000
+
+##
+## Load the payload from the ROM
+##
+default CONFIG_ROM_PAYLOAD = 1
+
+###
+### Defaults of options that you may want to override in the target config file
+###
+
+##
+## The default compiler
+##
+default CC="$(CROSS_COMPILE)gcc -m32"
+default HOSTCC="gcc"
+
+##
+## Disable the gdb stub by default
+##
+default CONFIG_GDB_STUB=0
+
+##
+## The Serial Console
+##
+
+# To Enable the Serial Console
+default CONFIG_CONSOLE_SERIAL8250=1
+
+## Select the serial console baud rate
+default TTYS0_BAUD=115200
+#default TTYS0_BAUD=57600
+#default TTYS0_BAUD=38400
+#default TTYS0_BAUD=19200
+#default TTYS0_BAUD=9600
+#default TTYS0_BAUD=4800
+#default TTYS0_BAUD=2400
+#default TTYS0_BAUD=1200
+
+# Select the serial console base port
+default TTYS0_BASE=0x3f8
+
+# Select the serial protocol
+# This defaults to 8 data bits, 1 stop bit, and no parity
+default TTYS0_LCS=0x3
+
+##
+### Select the coreboot loglevel
+##
+## EMERG 1 system is unusable
+## ALERT 2 action must be taken immediately
+## CRIT 3 critical conditions
+## ERR 4 error conditions
+## WARNING 5 warning conditions
+## NOTICE 6 normal but significant condition
+## INFO 7 informational
+## DEBUG 8 debug-level messages
+## SPEW 9 Way too many details
+
+## Request this level of debugging output
+default DEFAULT_CONSOLE_LOGLEVEL=8
+## At a maximum only compile in this level of debugging
+default MAXIMUM_CONSOLE_LOGLEVEL=8
+
+##
+## Select power on after power fail setting
+default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
+
+## Things we may not have
+default CONFIG_IDE=1
+
+default DEBUG=1
+# default CPU_OPT="-g"
+
+### End Options.lb
+#
+# ROMFS
+#
+#
+default CONFIG_ROMFS=0
+end
projects / coreboot.git / blobdiff