-##################################################################\r
-## BEGIN BOILERPLATE - DO NOT EDIT\r
-##\r
-## Compute the location and size of where this firmware image\r
-## (linuxBIOS plus payload) will live in the boot rom chip.\r
-##\r
-if USE_FALLBACK_IMAGE\r
-# The fallback image uses FALLBACK_SIZE bytes at the end of the ROM\r
-\r
- default ROM_SECTION_SIZE = FALLBACK_SIZE\r
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )\r
-\r
-else\r
-# The normal image goes at the beginning of the LinuxBIOS ROM region\r
-# and uses all the remaining space\r
-\r
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )\r
- default ROM_SECTION_OFFSET = 0\r
-end\r
-\r
-##\r
-## Compute where this copy of linuxBIOS will start in the boot rom\r
-##\r
-default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )\r
-\r
-##\r
-## Compute a range of ROM that can cached to speed up linuxBIOS,\r
-## execution speed.\r
-##\r
-## XIP_ROM_SIZE must be a power of 2.\r
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE\r
-default XIP_ROM_SIZE = 65536\r
-default XIP_ROM_BASE = ((( _ROMBASE + ROM_IMAGE_SIZE ) / XIP_ROM_SIZE ) * XIP_ROM_SIZE - XIP_ROM_SIZE )\r
-\r
-## END BOILERPLATE\r
-##################################################################\r
-\r
-arch i386 end \r
-\r
-##\r
-## Build the objects we have code for in this directory.\r
-##\r
-\r
-driver mainboard.o\r
-if HAVE_MP_TABLE object mptable.o end\r
-if HAVE_PIRQ_TABLE object irq_tables.o end\r
-if HAVE_ACPI_TABLES object acpi_tables.o end\r
-object reset.o\r
-\r
-# Include the VGA option ROM, but only if we're compiled to use it\r
-if CONFIG_PCI_ROM_RUN\r
- if CONFIG_CONSOLE_VGA \r
- object vgarom.S\r
- else\r
- object no_vgarom.S\r
- end\r
-else\r
- object no_vgarom.S\r
-end\r
-\r
-##\r
-## Romcc output\r
-##\r
-makerule ./failover.E\r
- depends "$(MAINBOARD)/failover.c ./romcc"\r
- action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"\r
-end\r
-\r
-makerule ./failover.inc\r
- depends "$(MAINBOARD)/failover.c ./romcc"\r
- action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"\r
-end\r
-\r
-makerule ./auto.E\r
- depends "$(MAINBOARD)/auto.c option_table.h ./romcc"\r
- action "./romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"\r
-end\r
-makerule ./auto.inc\r
- depends "$(MAINBOARD)/auto.c option_table.h ./romcc"\r
- action "./romcc -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"\r
-end\r
-\r
-##\r
-## Build our 16 bit and 32 bit linuxBIOS entry code\r
-##\r
-mainboardinit cpu/x86/16bit/entry16.inc\r
-mainboardinit cpu/x86/32bit/entry32.inc\r
-ldscript /cpu/x86/16bit/entry16.lds\r
-ldscript /cpu/x86/32bit/entry32.lds\r
-\r
-##\r
-## Build our reset vector (This is where linuxBIOS is entered)\r
-##\r
-if HAVE_FALLBACK_BOOT\r
- if USE_FALLBACK_IMAGE \r
- mainboardinit cpu/x86/16bit/reset16.inc \r
- ldscript /cpu/x86/16bit/reset16.lds\r
- else\r
- mainboardinit cpu/x86/32bit/reset32.inc \r
- ldscript /cpu/x86/32bit/reset32.lds \r
- end\r
-else\r
- mainboardinit cpu/x86/16bit/reset16.inc \r
- ldscript /cpu/x86/16bit/reset16.lds\r
-end\r
-\r
-### Should this be in the northbridge code?\r
-mainboardinit arch/i386/lib/cpu_reset.inc\r
-\r
-##\r
-## Include an id string (For safe flashing)\r
-##\r
-mainboardinit arch/i386/lib/id.inc\r
-ldscript /arch/i386/lib/id.lds\r
-\r
-###\r
-### This is the early phase of linuxBIOS startup \r
-### Things are delicate and we test to see if we should\r
-### failover to another image.\r
-###\r
-if USE_FALLBACK_IMAGE\r
- ldscript /arch/i386/lib/failover.lds \r
- mainboardinit ./failover.inc\r
-end\r
-\r
-###\r
-### O.k. We aren't just an intermediary anymore!\r
-###\r
-\r
-##\r
-## Setup RAM\r
-##\r
-mainboardinit cpu/x86/fpu/enable_fpu.inc\r
-mainboardinit cpu/x86/mmx/enable_mmx.inc\r
-mainboardinit cpu/x86/sse/enable_sse.inc\r
-mainboardinit ./auto.inc\r
-mainboardinit cpu/x86/sse/disable_sse.inc\r
-mainboardinit cpu/x86/mmx/disable_mmx.inc\r
-\r
-##\r
-## Include the secondary Configuration files \r
-##\r
-dir /pc80\r
-\r
-if CONFIG_CHIP_NAME\r
- config chip.h\r
-end\r
-\r
-# based on sample config for tyan/s2735\r
-chip northbridge/intel/e7501\r
- device pci_domain 0 on\r
- device pci 0.0 on end # Chipset host controller\r
- device pci 0.1 on end # Host RASUM controller\r
- device pci 2.0 on # Hub interface B\r
- chip southbridge/intel/i82870 # P64H2\r
- device pci 1c.0 on end # IOAPIC - bus B\r
- device pci 1d.0 on end # Hub to PCI-B bridge \r
- device pci 1e.0 on end # IOAPIC - bus A \r
- device pci 1f.0 on end # Hub to PCI-A bridge\r
- end\r
- end\r
- device pci 3.0 off end # Hub interface C (82808AA connector - disable for now)\r
- device pci 4.0 on # Hub interface D\r
- chip southbridge/intel/i82870 # P64H2\r
- device pci 1c.0 on end # IOAPIC - bus B\r
- device pci 1d.0 on end # Hub to PCI-B bridge\r
- device pci 1e.0 on end # IOAPIC - bus A\r
- device pci 1f.0 on end # Hub to PCI-A bridge\r
- end\r
- end\r
- device pci 6.0 on end # E7501 Power management registers? (undocumented)\r
- chip southbridge/intel/i82801ca\r
- device pci 1d.0 off end # USB (might not work, Southbridge code needs looking at)\r
- device pci 1d.1 off end # USB (not populated)\r
- device pci 1d.2 off end # USB (not populated)\r
- device pci 1e.0 on # Hub to PCI bridge\r
- chip drivers/pci/onboard # VGA ROM
- device pci 0.0 on end
- register "rom_address" = "_vgarom_start"
- end\r
- end
- device pci 1f.0 on # LPC bridge\r
- chip superio/smsc/lpc47b272\r
- device pnp 2e.0 off # Floppy\r
- io 0x60 = 0x3f0\r
- irq 0x70 = 6\r
- drq 0x74 = 2\r
- end\r
- device pnp 2e.3 off # Parallel Port\r
- io 0x60 = 0x378\r
- irq 0x70 = 7\r
- end\r
- device pnp 2e.4 on # Com1\r
- io 0x60 = 0x3f8\r
- irq 0x70 = 4\r
- end\r
- device pnp 2e.5 off # Com2\r
- io 0x60 = 0x2f8\r
- irq 0x70 = 3\r
- end\r
- device pnp 2e.7 on # Keyboard\r
- io 0x60 = 0x60\r
- io 0x62 = 0x64\r
- irq 0x70 = 1 # Keyboard interrupt\r
- irq 0x72 = 12 # Mouse interrupt\r
- end\r
- device pnp 2e.a off end # ACPI\r
- end\r
- end\r
- device pci 1f.1 on end # IDE\r
- device pci 1f.3 on end # SMBus\r
- device pci 1f.5 off end # AC97 Audio\r
- device pci 1f.6 off end # AC97 Modem\r
- end # SB\r
- end # PCI_DOMAIN\r
- device apic_cluster 0 on\r
- chip cpu/intel/socket_mPGA604_533Mhz\r
- device apic 0 on end\r
- end\r
- chip cpu/intel/socket_mPGA604_533Mhz\r
- device apic 6 on end\r
- end\r
- end\r
-end\r
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
+include /config/nofailovercalculation.lb
+
+arch i386 end
+
+##
+## Build the objects we have code for in this directory.
+##
+
+driver mainboard.o
+if CONFIG_GENERATE_MP_TABLE object mptable.o end
+if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
+if CONFIG_GENERATE_ACPI_TABLES object acpi_tables.o end
+object reset.o
+
+##
+## Romcc output
+##
+makerule ./failover.E
+ depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
+ action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
+end
+
+makerule ./failover.inc
+ depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
+ action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
+end
+
+makerule ./auto.E
+ depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+ action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
+end
+makerule ./auto.inc
+ depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+ action "../romcc -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
+end
+
+##
+## Build our 16 bit and 32 bit coreboot entry code
+##
+mainboardinit cpu/x86/16bit/entry16.inc
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/16bit/entry16.lds
+ldscript /cpu/x86/32bit/entry32.lds
+
+##
+## Build our reset vector (This is where coreboot is entered)
+##
+if CONFIG_HAVE_FALLBACK_BOOT
+ if CONFIG_USE_FALLBACK_IMAGE
+ mainboardinit cpu/x86/16bit/reset16.inc
+ ldscript /cpu/x86/16bit/reset16.lds
+ else
+ mainboardinit cpu/x86/32bit/reset32.inc
+ ldscript /cpu/x86/32bit/reset32.lds
+ end
+else
+ mainboardinit cpu/x86/16bit/reset16.inc
+ ldscript /cpu/x86/16bit/reset16.lds
+end
+
+### Should this be in the northbridge code?
+mainboardinit arch/i386/lib/cpu_reset.inc
+
+##
+## Include an id string (For safe flashing)
+##
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
+
+###
+### This is the early phase of coreboot startup
+### Things are delicate and we test to see if we should
+### failover to another image.
+###
+if CONFIG_USE_FALLBACK_IMAGE
+ ldscript /arch/i386/lib/failover.lds
+ mainboardinit ./failover.inc
+end
+
+###
+### O.k. We aren't just an intermediary anymore!
+###
+
+##
+## Setup RAM
+##
+mainboardinit cpu/x86/fpu/enable_fpu.inc
+mainboardinit cpu/x86/mmx/enable_mmx.inc
+mainboardinit cpu/x86/sse/enable_sse.inc
+mainboardinit ./auto.inc
+mainboardinit cpu/x86/sse/disable_sse.inc
+mainboardinit cpu/x86/mmx/disable_mmx.inc
+
+##
+## Include the secondary Configuration files
+##
+dir /pc80
+
+config chip.h
+
+# based on sample config for tyan/s2735
+chip northbridge/intel/e7501
+ device pci_domain 0 on
+ device pci 0.0 on end # Chipset host controller
+ device pci 0.1 on end # Host RASUM controller
+ device pci 2.0 on # Hub interface B
+ chip southbridge/intel/i82870 # P64H2
+ device pci 1c.0 on end # IOAPIC - bus B
+ device pci 1d.0 on end # Hub to PCI-B bridge
+ device pci 1e.0 on end # IOAPIC - bus A
+ device pci 1f.0 on end # Hub to PCI-A bridge
+ end
+ end
+ device pci 3.0 off end # Hub interface C (82808AA connector - disable for now)
+ device pci 4.0 on # Hub interface D
+ chip southbridge/intel/i82870 # P64H2
+ device pci 1c.0 on end # IOAPIC - bus B
+ device pci 1d.0 on end # Hub to PCI-B bridge
+ device pci 1e.0 on end # IOAPIC - bus A
+ device pci 1f.0 on end # Hub to PCI-A bridge
+ end
+ end
+ device pci 6.0 on end # E7501 Power management registers? (undocumented)
+ chip southbridge/intel/i82801ca
+ device pci 1d.0 off end # USB (might not work, Southbridge code needs looking at)
+ device pci 1d.1 off end # USB (not populated)
+ device pci 1d.2 off end # USB (not populated)
+ device pci 1e.0 on # Hub to PCI bridge
+ chip drivers/pci/onboard # VGA ROM
+ device pci 0.0 on end
+ end
+ end
+ device pci 1f.0 on # LPC bridge
+ chip superio/smsc/lpc47b272
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.3 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.4 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.5 off # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.7 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1 # Keyboard interrupt
+ irq 0x72 = 12 # Mouse interrupt
+ end
+ device pnp 2e.a off end # ACPI
+ end
+ end
+ device pci 1f.1 on end # IDE
+ device pci 1f.3 on end # SMBus
+ device pci 1f.5 off end # AC97 Audio
+ device pci 1f.6 off end # AC97 Modem
+ end # SB
+ end # PCI_DOMAIN
+ device apic_cluster 0 on
+ chip cpu/intel/socket_mPGA604
+ device apic 0 on end
+ end
+ chip cpu/intel/socket_mPGA604
+ device apic 6 on end
+ end
+ end
+end
projects / coreboot.git / blobdiff