Simplify a few code chunks, fix whitespace and indentation.

[coreboot.git] / src / mainboard / intel / truxton / romstage.c

diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c
index da48be39b9443b817187a21a2847e172bbba21f0..c75ce3e732af7c6f423621d63ca6ddb80230461f 100644 (file)
--- a/src/mainboard/intel/truxton/romstage.c
+++ b/src/mainboard/intel/truxton/romstage.c
@@ -37,7 +37,7 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "superio/intel/i3100/i3100_early_serial.c"
 #include "cpu/x86/bist.h"
-#include "spd.h"
+#include <spd.h>
 
 #define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0 | DEVPRES_D4F0)
 
@@ -61,16 +61,15 @@ static void main(unsigned long bist)
                {
                        .node_id = 0,
                        .f0 = PCI_DEV(0, 0x00, 0),
-                       .channel0 = { (0xa<<3)|2, (0xa<<3)|3 },
+                       .channel0 = { DIMM2, DIMM3 },
                }
        };
 
        if (bist == 0) {
                /* Skip this if there was a built in self test failure */
                early_mtrr_init();
-               if (memory_initialized()) {
+               if (memory_initialized())
                        skip_romstage();
-               }
        }
 
        /* Set up the console */
@@ -105,4 +104,3 @@ static void main(unsigned long bist)
        ram_verify(0x00000000, 0x02000000);
 #endif
 }
-