Restructure i3100 Super I/O driver to match the rest of the codebase.

[coreboot.git] / src / mainboard / intel / truxton / romstage.c

diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c
index b2e04be896e6a74be8b4ad12c381f9a2e984a781..4f85095d9fe67ad57ef0a1270562afdbc4a37e07 100644 (file)
--- a/src/mainboard/intel/truxton/romstage.c
+++ b/src/mainboard/intel/truxton/romstage.c
@@ -15,7 +15,6 @@
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- *
  */
 
 #include <stdint.h>
@@ -26,10 +25,9 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
+#include <pc80/mc146818rtc.h>
 #include "pc80/udelay_io.c"
-#include "arch/i386/lib/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i3100/i3100_early_smbus.c"
 #include "southbridge/intel/i3100/i3100_early_lpc.c"
@@ -41,15 +39,8 @@
 #include "cpu/x86/bist.h"
 #include "spd.h"
 
-#define SIO_GPIO_BASE 0x680
-#define SIO_XBUS_BASE 0x4880
-
 #define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0 | DEVPRES_D4F0)
 
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-       /* nothing to do */
-}
 static inline int spd_read_byte(u16 device, u8 address)
 {
        return smbus_read_byte(device, address);
@@ -58,9 +49,12 @@ static inline int spd_read_byte(u16 device, u8 address)
 #include "northbridge/intel/i3100/raminit_ep80579.c"
 #include "lib/generic_sdram.c"
 #include "../../intel/jarrell/debug.c"
+#include "arch/i386/lib/stages.c"
 
 /* #define TRUXTON_DEBUG */
 
+#define SERIAL_DEV PNP_DEV(0x4e, I3100_SP1)
+
 static void main(unsigned long bist)
 {
        msr_t msr;
@@ -77,13 +71,15 @@ static void main(unsigned long bist)
                /* Skip this if there was a built in self test failure */
                early_mtrr_init();
                if (memory_initialized()) {
-                       asm volatile ("jmp __cpu_reset");
+                       skip_romstage();
                }
        }
 
        /* Set up the console */
        i3100_enable_superio();
-       i3100_enable_serial(I3100_SUPERIO_CONFIG_PORT, I3100_SP1, CONFIG_TTYS0_BASE);
+       i3100_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+       i3100_configure_uart_clk(SERIAL_DEV, I3100_UART_CLK_PREDIVIDE_26);
+
        uart_init();
        console_init();