Restructure i3100 Super I/O driver to match the rest of the codebase.

[coreboot.git] / src / mainboard / intel / mtarvon / romstage.c

diff --git a/src/mainboard/intel/mtarvon/romstage.c b/src/mainboard/intel/mtarvon/romstage.c
index cdd0ed55732046827a4b12c493220928b82c0111..f36e4a4e681568957528ebc3bdd7b8883ca53382 100644 (file)
--- a/src/mainboard/intel/mtarvon/romstage.c
+++ b/src/mainboard/intel/mtarvon/romstage.c
@@ -28,7 +28,6 @@
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "southbridge/intel/i3100/i3100_early_smbus.c"
 #include "southbridge/intel/i3100/i3100_early_lpc.c"
 #include "northbridge/intel/i3100/raminit.h"
@@ -38,12 +37,11 @@
 #include "northbridge/intel/i3100/memory_initialized.c"
 #include "cpu/x86/bist.h"
 
-#define SIO_GPIO_BASE 0x680
-#define SIO_XBUS_BASE 0x4880
-
 #define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0)
 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
 
+#define SERIAL_DEV PNP_DEV(0x4e, I3100_SP1)
+
 static inline int spd_read_byte(u16 device, u8 address)
 {
        return smbus_read_byte(device, address);
@@ -79,9 +77,12 @@ void main(unsigned long bist)
                }
 #endif
        }
+
        /* Set up the console */
        i3100_enable_superio();
-       i3100_enable_serial(0x4e, I3100_SP1, CONFIG_TTYS0_BASE);
+       i3100_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+       i3100_configure_uart_clk(SERIAL_DEV, I3100_UART_CLK_PREDIVIDE_26);
+
        uart_init();
        console_init();