Restructure i3100 Super I/O driver to match the rest of the codebase.

[coreboot.git] / src / mainboard / intel / mtarvon / romstage.c

diff --git a/src/mainboard/intel/mtarvon/romstage.c b/src/mainboard/intel/mtarvon/romstage.c
index 6524ea217ca9f7f99a69301d52ca1966215ed9fc..f36e4a4e681568957528ebc3bdd7b8883ca53382 100644 (file)
--- a/src/mainboard/intel/mtarvon/romstage.c
+++ b/src/mainboard/intel/mtarvon/romstage.c
@@ -18,8 +18,6 @@
  *
  */
 
-#define ASSEMBLY 1
-#define __PRE_RAM__
 #include <stdint.h>
 #include <stdlib.h>
 #include <device/pci_def.h>
@@ -28,30 +26,22 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include "lib/ramtest.c"
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
 #include "southbridge/intel/i3100/i3100_early_smbus.c"
 #include "southbridge/intel/i3100/i3100_early_lpc.c"
 #include "northbridge/intel/i3100/raminit.h"
 #include "superio/intel/i3100/i3100.h"
-#include "cpu/x86/lapic/boot_cpu.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "superio/intel/i3100/i3100_early_serial.c"
 #include "northbridge/intel/i3100/memory_initialized.c"
 #include "cpu/x86/bist.h"
 
-#define SIO_GPIO_BASE 0x680
-#define SIO_XBUS_BASE 0x4880
-
 #define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0)
 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
 
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-       /* nothing to do */
-}
+#define SERIAL_DEV PNP_DEV(0x4e, I3100_SP1)
+
 static inline int spd_read_byte(u16 device, u8 address)
 {
        return smbus_read_byte(device, address);
@@ -59,10 +49,11 @@ static inline int spd_read_byte(u16 device, u8 address)
 
 #include "northbridge/intel/i3100/raminit.c"
 #include "lib/generic_sdram.c"
-#include "../jarrell/debug.c"
+#if 0 /* skip_romstage doesn't compile with gcc */
+#include "arch/i386/lib/stages.c"
+#endif
 
-
-static void main(unsigned long bist)
+void main(unsigned long bist)
 {
        msr_t msr;
        u16 perf;
@@ -79,15 +70,19 @@ static void main(unsigned long bist)
        };
 
        if (bist == 0) {
+#if 0 /* skip_romstage doesn't compile with gcc */
                /* Skip this if there was a built in self test failure */
-               early_mtrr_init();
                if (memory_initialized()) {
-                       asm volatile ("jmp __cpu_reset");
+                       skip_romstage();
                }
+#endif
        }
+
        /* Set up the console */
        i3100_enable_superio();
-       i3100_enable_serial(0x4e, I3100_SP1, CONFIG_TTYS0_BASE);
+       i3100_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+       i3100_configure_uart_clk(SERIAL_DEV, I3100_UART_CLK_PREDIVIDE_26);
+
        uart_init();
        console_init();
 
@@ -126,3 +121,4 @@ static void main(unsigned long bist)
 
        ram_check(0, 1024 * 1024);
 }
+