Move "select CACHE_AS_RAM" lines from boards into CPU socket.

[coreboot.git] / src / mainboard / intel / mtarvon / Kconfig

diff --git a/src/mainboard/intel/mtarvon/Kconfig b/src/mainboard/intel/mtarvon/Kconfig
index 255ddc393dbb3d921398154923155fc42e439590..76dec5eb374d2cee4e488fdb2ccae6ac5daa0a9e 100644 (file)
--- a/src/mainboard/intel/mtarvon/Kconfig
+++ b/src/mainboard/intel/mtarvon/Kconfig
@@ -1,41 +1,48 @@
-config BOARD_INTEL_MTARVON
-       bool "Mt. Arvon"
+if BOARD_INTEL_MTARVON
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+       def_bool y
        select ARCH_X86
        select CPU_INTEL_SOCKET_MPGA479M
        select NORTHBRIDGE_INTEL_I3100
        select SOUTHBRIDGE_INTEL_I3100
        select SUPERIO_INTEL_I3100
+       select HAVE_HARD_RESET
        select HAVE_PIRQ_TABLE
+       select HAVE_MP_TABLE
        select UDELAY_TSC
-       help
-          Intel Mt. Arvon mainboard.
+       select BOARD_ROMSIZE_KB_2048
 
 config MAINBOARD_DIR
        string
        default intel/mtarvon
-       depends on BOARD_INTEL_MTARVON
-
-config LB_CKS_RANGE_END
-       int
-       default 122
-       depends on BOARD_INTEL_MTARVON
-
-config LB_CKS_LOC
-       int
-       default 123
-       depends on BOARD_INTEL_MTARVON
 
 config MAINBOARD_PART_NUMBER
        string
-       default "Mt. Arvon"
-       depends on BOARD_INTEL_MTARVON
-
-config HAVE_OPTION_TABLE
-       bool
-       default n
-       depends on BOARD_INTEL_MTARVON
+       default "3100 devkit (Mt. Arvon)"
 
 config IRQ_SLOT_COUNT
        int
        default 1
-       depends on BOARD_INTEL_MTARVON
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+       hex
+       default 0x8086
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+       hex
+       default 0x2680
+
+config DCACHE_RAM_BASE
+       hex
+       default 0xffdf8000
+
+config DCACHE_RAM_SIZE
+       hex
+       default 0x8000
+
+config MAX_CPUS
+       int
+       default 4
+
+endif # BOARD_INTEL_MTARVON