#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
#include <console/console.h>
#include "lib/ramtest.c"
#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
#include "superio/nsc/pc87427/pc87427_early_init.c"
#include "northbridge/intel/e7520/memory_initialized.c"
#include "cpu/x86/bist.h"
+#include <spd.h>
#define SIO_GPIO_BASE 0x680
#define SIO_XBUS_BASE 0x4880
#define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D6F0)
#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
-/* Beta values: 0x00090800 */
-/* Silver values: 0x000a0900 */
-#define RECVENA_CONFIG 0x000a090a
-#define RECVENB_CONFIG 0x000a090a
-#define DIMM_MAP_LOGICAL 0x0124
-
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
static void main(unsigned long bist)
{
- /*
- *
- *
- */
static const struct mem_controller mch[] = {
{
.node_id = 0,
.f2 = PCI_DEV(0, 0x00, 2),
.f3 = PCI_DEV(0, 0x00, 3),
*/
- .channel0 = { (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, 0 },
- .channel1 = { (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, 0 },
+ .channel0 = { DIMM2, DIMM1, DIMM0, 0 },
+ .channel1 = { DIMM6, DIMM5, DIMM4, 0 },
}
};
skip_romstage();
}
}
+
/* Setup the console */
pc87427_disable_dev(CONSOLE_SERIAL_DEV);
pc87427_disable_dev(HIDDEN_SERIAL_DEV);
ram_check(0x00000000, 0x02000000);
#endif
-#endif
-#if 0
- while(1) {
- hlt();
- }
#endif
}
-