Simplify a few code chunks, fix whitespace and indentation.

[coreboot.git] / src / mainboard / intel / eagleheights / romstage.c

diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c
index 072dad67f847c5620cef211e7ff0b2b4e3949aae..8f8cd0f00fce34b7665e09f32a9f43f2360524ed 100644 (file)
--- a/src/mainboard/intel/eagleheights/romstage.c
+++ b/src/mainboard/intel/eagleheights/romstage.c
@@ -21,40 +21,27 @@
  */
 
 #include <delay.h>
-
 #include <stdint.h>
 #include <arch/io.h>
 #include <arch/romcc_io.h>
 #include <device/pci_def.h>
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
-
 #include <pc80/mc146818rtc.h>
-
 #include <console/console.h>
 #include <cpu/x86/bist.h>
-
+#include <cpu/intel/acpi.h>
 #include "southbridge/intel/i3100/i3100_early_smbus.c"
 #include "southbridge/intel/i3100/i3100_early_lpc.c"
 #include "reset.c"
 #include "superio/intel/i3100/i3100_early_serial.c"
 #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
 #include "northbridge/intel/i3100/i3100.h"
+#include "southbridge/intel/i3100/i3100.h"
 
 #define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0)
 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
 
-#define IA32_PERF_STS     0x198
-#define IA32_PERF_CTL     0x199
-#define MSR_THERM2_CTL    0x19D
-#define IA32_MISC_ENABLES 0x1A0
-
-/* SATA */
-#define SATA_MAP 0x90
-
-#define SATA_MODE_IDE  0x00
-#define SATA_MODE_AHCI 0x01
-
 #define RCBA_RPC   0x0224 /* 32 bit */
 
 #define RCBA_TCTL  0x3000 /*  8 bit */
@@ -87,6 +74,7 @@ static inline int spd_read_byte(u16 device, u8 address)
 #include "lib/generic_sdram.c"
 #include "northbridge/intel/i3100/reset_test.c"
 #include "debug.c"
+#include <spd.h>
 
 #define SERIAL_DEV PNP_DEV(0x4e, I3100_SP1)
 
@@ -145,14 +133,13 @@ void main(unsigned long bist)
                        .f1 = PCI_DEV(0, 0x00, 1),
                        .f2 = PCI_DEV(0, 0x00, 2),
                        .f3 = PCI_DEV(0, 0x00, 3),
-                       .channel0 = { (0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0 },
-                       .channel1 = { (0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4 },
+                       .channel0 = { DIMM3, DIMM2, DIMM1, DIMM0 },
+                       .channel1 = { DIMM7, DIMM6, DIMM5, DIMM4 },
                }
        };
 
-       if (bist == 0) {
+       if (bist == 0)
                enable_lapic();
-       }
 
        /* Setup the console */
        i3100_enable_superio();
@@ -204,4 +191,3 @@ void main(unsigned long bist)
        /* Initialize memory */
        sdram_initialize(ARRAY_SIZE(mch), mch);
 }
-