Restructure i3100 Super I/O driver to match the rest of the codebase.
[coreboot.git] / src / mainboard / intel / eagleheights / romstage.c
index cc6966b074f17e844bfe2332590396f736e718d9..8e1d21236330d7eb50d3fd2a707a601b44736c3d 100644 (file)
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
 
 #include <console/console.h>
 #include <cpu/x86/bist.h>
 
-#include "lib/ramtest.c"
 #include "southbridge/intel/i3100/i3100_early_smbus.c"
 #include "southbridge/intel/i3100/i3100_early_lpc.c"
 #include "reset.c"
 #include "superio/intel/i3100/i3100_early_serial.c"
 #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
 
-/* Data */
-#define UART_RBR 0x00
-#define UART_TBR 0x00
-
-/* Control */
-#define UART_IER 0x01
-#define UART_IIR 0x02
-#define UART_FCR 0x02
-#define UART_LCR 0x03
-#define UART_MCR 0x04
-#define UART_DLL 0x00
-#define UART_DLM 0x01
-
-/* Status */
-#define UART_LSR 0x05
-#define UART_MSR 0x06
-#define UART_SCR 0x07
-
-#define SIO_GPIO_BASE 0x680
-#define SIO_XBUS_BASE 0x4880
-
 #define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0)
 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
 
@@ -114,6 +91,8 @@ static inline int spd_read_byte(u16 device, u8 address)
 #include "northbridge/intel/i3100/reset_test.c"
 #include "debug.c"
 
+#define SERIAL_DEV PNP_DEV(0x4e, I3100_SP1)
+
 static void early_config(void)
 {
        u32 gcs, rpc, fd;
@@ -180,7 +159,9 @@ void main(unsigned long bist)
 
        /* Setup the console */
        i3100_enable_superio();
-       i3100_enable_serial(0x4E, I3100_SP1, CONFIG_TTYS0_BASE);
+       i3100_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+       i3100_configure_uart_clk(SERIAL_DEV, I3100_UART_CLK_PREDIVIDE_26);
+
        uart_init();
        console_init();