* MA 02110-1301 USA
*/
-
#include <console/console.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include <arch/smp/mpspec.h>
#include <device/pci.h>
#include <string.h>
#define RCBA_D29IR 0x3144
#define RCBA_D28IR 0x3146
-void *smp_write_config_table(void *v)
+static void *smp_write_config_table(void *v)
{
- static const char sig[4] = "PCMP";
- static const char oem[8] = "Intel ";
- static const char productid[12] = "EagleHeights";
struct mp_config_table *mc;
unsigned char bus_num, bus_chipset, bus_isa, bus_pci;
unsigned char bus_pcie_a, bus_pcie_a1, bus_pcie_b;
dev = dev_find_slot(0, PCI_DEVFN(0x1F,0));
res = find_resource(dev, RCBA);
if (!res) {
- return;
+ return NULL;
}
rcba = res->base;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
- memset(mc, 0, sizeof(*mc));
-
- memcpy(mc->mpc_signature, sig, sizeof(sig));
- mc->mpc_length = sizeof(*mc); /* initially just the header */
- mc->mpc_spec = 0x04;
- mc->mpc_checksum = 0; /* not yet computed */
- memcpy(mc->mpc_oem, oem, sizeof(oem));
- memcpy(mc->mpc_productid, productid, sizeof(productid));
- mc->mpc_oemptr = 0;
- mc->mpc_oemsize = 0;
- mc->mpc_entry_count = 0; /* No entries yet... */
- mc->mpc_lapic = LAPIC_ADDR;
- mc->mpe_length = 0;
- mc->mpe_checksum = 0;
- mc->reserved = 0;
+
+ mptable_init(mc, "EagleHeights", LAPIC_ADDR);
smp_write_processors(mc);
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++;
} else {
- printk_debug("ERROR - could not find PCI 0:1e.0, using defaults\n");
+ printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n");
bus_pci = 6;
bus_isa = 7;
}
if(dev) {
bus_pcie_a = pci_read_config8(dev, PCI_SECONDARY_BUS);
} else {
- printk_debug("ERROR - could not find PCIe Port A 0:2.0, using defaults\n");
+ printk(BIOS_DEBUG, "ERROR - could not find PCIe Port A 0:2.0, using defaults\n");
bus_pcie_a = 1;
}
if(dev) {
bus_pcie_a1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
} else {
- printk_debug("ERROR - could not find PCIe Port B 0:3.0, using defaults\n");
+ printk(BIOS_DEBUG, "ERROR - could not find PCIe Port B 0:3.0, using defaults\n");
bus_pcie_a1 = 2;
}
if(dev) {
bus_pcie_b = pci_read_config8(dev, PCI_SECONDARY_BUS);
} else {
- printk_debug("ERROR - could not find PCIe Port B 0:3.0, using defaults\n");
+ printk(BIOS_DEBUG, "ERROR - could not find PCIe Port B 0:3.0, using defaults\n");
bus_pcie_b = 3;
}
smp_write_bus(mc, bus_isa, "ISA ");
/*I/O APICs: APIC ID Version State Address*/
- smp_write_ioapic(mc, 2, 0x20, 0xfec00000);
- /*
- {
- device_t dev;
- struct resource *res;
- dev = dev_find_slot(1, PCI_DEVFN(0x1e,0));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- smp_write_ioapic(mc, 3, 0x20, res->base);
- }
- }
- dev = dev_find_slot(1, PCI_DEVFN(0x1c,0));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- smp_write_ioapic(mc, 4, 0x20, res->base);
- }
- }
- dev = dev_find_slot(4, PCI_DEVFN(0x1e,0));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- smp_write_ioapic(mc, 5, 0x20, res->base);
- }
- }
- dev = dev_find_slot(4, PCI_DEVFN(0x1c,0));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- smp_write_ioapic(mc, 8, 0x20, res->base);
- }
- }
- }
- */
- /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
- /* IRQ0 8254 Counter 0, MNT0 */
- smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0, IO_APIC0, 0);
- /* IRQ1 Keyboard */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 1, IO_APIC0, 1);
- /* IRQ2 8259 cascade only */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0, IO_APIC0, 2);
- /* IRQ3 COM2, Option for PIRQx */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 3, IO_APIC0, 3);
- /* IRQ4 COM1, Option for PIRQx */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 4, IO_APIC0, 4);
- /* IRQ5 Option for PIRQx */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 5, IO_APIC0, 5);
- /* IRQ6 Option for PIRQx */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 6, IO_APIC0, 6);
- /* IRQ7 OPtion for PIRQx */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 7, IO_APIC0, 7);
- /* IRQ8# RTC, MNT1 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, bus_isa, 8, IO_APIC0, 8);
- /* IRQ9 Option for PIRQx, SCI, TCO */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 9, IO_APIC0, 9);
- /* IRQ10 Option for PIRQx, SCI, TCO */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 12, IO_APIC0, 10);
- /* IRQ11 Option for PIRQx, SCI, TCO, MMT2 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 12, IO_APIC0, 11);
- /* IRQ12 Mouse, Option for PIRQx */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 12, IO_APIC0, 12);
- /* IRQ13 Floating point interrupt generated off of the processor assertion of FERR# */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 13, IO_APIC0, 13);
- /* IRQ14 PIRQx Sata primary (legacy mode) */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 14, IO_APIC0, 14);
- /* IRQ15 PIRQx Sata secondary (legacy mode) */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 15, IO_APIC0, 15);
+ smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
+
+ mptable_add_isa_interrupts(mc, bus_isa, IO_APIC0, 0);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
- smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0, MP_APIC_ALL, 0);
- smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0, MP_APIC_ALL, 1);
+ smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0, MP_APIC_ALL, 0);
+ smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0, MP_APIC_ALL, 1);
/* Internal PCI device for i3100 */
/* Compute the checksums */
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
- printk_debug("Wrote the mp table end at: %p - %p\n",
+ printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
mc, smp_next_mpe_entry(mc));
return smp_next_mpe_entry(mc);
}
projects / coreboot.git / blobdiff