remove usbdebug.h include from mainboard/romstage code

[coreboot.git] / src / mainboard / intel / d945gclf / romstage.c

diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c
index f7056737dc462b7181c670a490d461456afb463d..a4cb3b2ac1d04392441685517b9f6d81764451c5 100644 (file)
--- a/src/mainboard/intel/d945gclf/romstage.c
+++ b/src/mainboard/intel/d945gclf/romstage.c
@@ -30,7 +30,6 @@
 #include "superio/smsc/lpc47m15x/lpc47m15x.h"
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include <usbdebug.h>
 #include <cpu/x86/bist.h>
 #include "superio/smsc/lpc47m15x/early_serial.c"
 #include "northbridge/intel/i945/i945.h"
@@ -198,13 +197,6 @@ void main(unsigned long bist)
        early_superio_config_lpc47m15x();
 
        /* Set up the console */
-       uart_init();
-
-#if CONFIG_USBDEBUG
-       i82801gx_enable_usbdebug(1);
-       early_usbdebug_init();
-#endif
-
        console_init();
 
        /* Halt if there was a built in self test failure */
@@ -243,7 +235,7 @@ void main(unsigned long bist)
        dump_spd_registers();
 #endif
 
-       sdram_initialize(boot_mode);
+       sdram_initialize(boot_mode, NULL);
 
        /* Perform some initialization that must run before stage2 */
        early_ich7_init();
@@ -297,7 +289,7 @@ void main(unsigned long bist)
                        memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
 
                /* Magic for S3 resume */
-               pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
+               pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC);
        }
 #endif
 }