remove usbdebug.h include from mainboard/romstage code

[coreboot.git] / src / mainboard / intel / d945gclf / romstage.c

diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c
index 961069a59acf595e969d679586f6f1f304b62546..a4cb3b2ac1d04392441685517b9f6d81764451c5 100644 (file)
--- a/src/mainboard/intel/d945gclf/romstage.c
+++ b/src/mainboard/intel/d945gclf/romstage.c
@@ -19,10 +19,6 @@
 
 // __PRE_RAM__ means: use "unsigned" for device, not a struct.
 
-/* Configuration of the i945 driver */
-#define CHIPSET_I945GC 1
-#define CHANNEL_XOR_RANDOMIZATION 1
-
 #include <stdint.h>
 #include <string.h>
 #include <arch/io.h>
@@ -30,31 +26,19 @@
 #include <device/pci_def.h>
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
-
+#include <lib.h>
 #include "superio/smsc/lpc47m15x/lpc47m15x.h"
-
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-
+#include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/x86/bist.h>
-
-#if CONFIG_USBDEBUG_DIRECT
-#define DBGP_DEFAULT 1
-#include "southbridge/intel/i82801gx/i82801gx_usb_debug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
-
-#include "lib/ramtest.c"
-#include "southbridge/intel/i82801gx/i82801gx_early_smbus.c"
-#include "superio/smsc/lpc47m15x/lpc47m15x_early_serial.c"
-
-#include "northbridge/intel/i945/udelay.c"
+#include "superio/smsc/lpc47m15x/early_serial.c"
+#include "northbridge/intel/i945/i945.h"
+#include "northbridge/intel/i945/raminit.h"
+#include "southbridge/intel/i82801gx/i82801gx.h"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1)
 
-#include "southbridge/intel/i82801gx/i82801gx.h"
-static void setup_ich7_gpios(void)
+void setup_ich7_gpios(void)
 {
        /* TODO: This is highly board specific and should be moved */
        printk(BIOS_DEBUG, " GPIOS...");
@@ -71,18 +55,6 @@ static void setup_ich7_gpios(void)
        outl(0x000300fd, DEFAULT_GPIOBASE + 0x38);      /* GP_LVL */
 }
 
-#include "northbridge/intel/i945/early_init.c"
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-       return smbus_read_byte(device, address);
-}
-
-#include "northbridge/intel/i945/raminit.h"
-#include "northbridge/intel/i945/raminit.c"
-#include "northbridge/intel/i945/errata.c"
-#include "northbridge/intel/i945/debug.c"
-
 static void ich7_enable_lpc(void)
 {
        // Enable Serial IRQ
@@ -213,34 +185,18 @@ static void early_ich7_init(void)
 
 #include <cbmem.h>
 
-// Now, this needs to be included because it relies on the symbol
-// __PRE_RAM__ being set during CAR stage (in order to compile the
-// BSS free versions of the functions). Either rewrite the code
-// to be always BSS free, or invent a flag that's better suited than
-// __PRE_RAM__ to determine whether we're in ram init stage (stage 1)
-//
-#include "lib/cbmem.c"
-
 void main(unsigned long bist)
 {
        u32 reg32;
        int boot_mode = 0;
 
-       if (bist == 0) {
+       if (bist == 0)
                enable_lapic();
-       }
 
        ich7_enable_lpc();
        early_superio_config_lpc47m15x();
 
        /* Set up the console */
-       uart_init();
-
-#if CONFIG_USBDEBUG_DIRECT
-       i82801gx_enable_usbdebug_direct(DBGP_DEFAULT);
-       early_usbdebug_direct_init();
-#endif
-
        console_init();
 
        /* Halt if there was a built in self test failure */
@@ -279,7 +235,7 @@ void main(unsigned long bist)
        dump_spd_registers();
 #endif
 
-       sdram_initialize(boot_mode);
+       sdram_initialize(boot_mode, NULL);
 
        /* Perform some initialization that must run before stage2 */
        early_ich7_init();
@@ -297,7 +253,7 @@ void main(unsigned long bist)
 
 #if !CONFIG_HAVE_ACPI_RESUME
 #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
-#if defined(DEBUG_RAM_SETUP)
+#if CONFIG_DEBUG_RAM_SETUP
        sdram_dump_mchbar_registers();
 #endif
 
@@ -333,8 +289,7 @@ void main(unsigned long bist)
                        memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
 
                /* Magic for S3 resume */
-               pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
+               pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC);
        }
 #endif
 }
-