/*
* This file is part of the coreboot project.
- *
+ *
* Copyright (C) 2007-2008 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
*/
// __PRE_RAM__ means: use "unsigned" for device, not a struct.
-#define __PRE_RAM__
-
-/* Configuration of the i945 driver */
-#define CHIPSET_I945GC 1
-#define CHANNEL_XOR_RANDOMIZATION 1
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
-
+#include <lib.h>
#include "superio/smsc/lpc47m15x/lpc47m15x.h"
-
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include <usbdebug.h>
#include <cpu/x86/bist.h>
-
-#if CONFIG_USBDEBUG_DIRECT
-#define DBGP_DEFAULT 1
-#include "southbridge/intel/i82801gx/i82801gx_usb_debug.c"
-#include "pc80/usbdebug_direct_serial.c"
-#endif
-
-#include "lib/ramtest.c"
-#include "southbridge/intel/i82801gx/i82801gx_early_smbus.c"
#include "superio/smsc/lpc47m15x/lpc47m15x_early_serial.c"
-
-#include "northbridge/intel/i945/udelay.c"
+#include "northbridge/intel/i945/i945.h"
+#include "northbridge/intel/i945/raminit.h"
+#include "southbridge/intel/i82801gx/i82801gx.h"
#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1)
-#include "southbridge/intel/i82801gx/i82801gx.h"
-static void setup_ich7_gpios(void)
+void enable_smbus(void);
+
+void setup_ich7_gpios(void)
{
/* TODO: This is highly board specific and should be moved */
- printk_debug(" GPIOS...");
+ printk(BIOS_DEBUG, " GPIOS...");
/* General Registers */
outl(0x3f3df7c1, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */
outl(0xc6fcbfc3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */
outl(0x000300fd, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */
}
-#include "northbridge/intel/i945/early_init.c"
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include "northbridge/intel/i945/raminit.h"
-#include "northbridge/intel/i945/raminit.c"
-#include "northbridge/intel/i945/reset_test.c"
-#include "northbridge/intel/i945/errata.c"
-#include "northbridge/intel/i945/debug.c"
-
static void ich7_enable_lpc(void)
{
// Enable Serial IRQ
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c0681);
}
-
/* This box has two superios, so enabling serial becomes slightly excessive.
* We disable a lot of stuff to make sure that there are no conflicts between
* the two. Also set up the GPIOs from the beginning. This is the "no schematic
static void early_superio_config_lpc47m15x(void)
{
device_t dev;
-
+
dev=PNP_DEV(0x2e, LPC47M15X_SP1);
pnp_enter_conf_state(dev);
RCBA32(0x2034) = reg32;
}
-#include "southbridge/intel/i82801gx/cmos_failover.c"
-
#include <cbmem.h>
// Now, this needs to be included because it relies on the symbol
//
#include "lib/cbmem.c"
-void real_main(unsigned long bist)
+void main(unsigned long bist)
{
u32 reg32;
int boot_mode = 0;
/* Set up the console */
uart_init();
-#if CONFIG_USBDEBUG_DIRECT
- i82801gx_enable_usbdebug_direct(DBGP_DEFAULT);
- early_usbdebug_direct_init();
+#if CONFIG_USBDEBUG
+ i82801gx_enable_usbdebug(1);
+ early_usbdebug_init();
#endif
console_init();
report_bist_failure(bist);
if (MCHBAR16(SSKPD) == 0xCAFE) {
- printk_debug("soft reset detected.\n");
+ printk(BIOS_DEBUG, "soft reset detected.\n");
boot_mode = 1;
}
/* Read PM1_CNT */
reg32 = inl(DEFAULT_PMBASE + 0x04);
- printk_debug("PM1_CNT: %08x\n", reg32);
+ printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
if (((reg32 >> 10) & 7) == 5) {
#if CONFIG_HAVE_ACPI_RESUME
- printk_debug("Resume from S3 detected.\n");
+ printk(BIOS_DEBUG, "Resume from S3 detected.\n");
boot_mode = 2;
/* Clear SLP_TYPE. This will break stage2 but
* we care for that when we get there.
*/
outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
#else
- printk_debug("Resume from S3 detected, but disabled.\n");
+ printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
#endif
}
/* Enable SPD ROMs and DDR-II DRAM */
enable_smbus();
-
+
#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
dump_spd_registers();
#endif
/* Perform some initialization that must run before stage2 */
early_ich7_init();
- /* This should probably go away. Until now it is required
- * and mainboard specific
+ /* This should probably go away. Until now it is required
+ * and mainboard specific
*/
rcba_config();
#if !CONFIG_HAVE_ACPI_RESUME
#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
-#if defined(DEBUG_RAM_SETUP)
+#if CONFIG_DEBUG_RAM_SETUP
sdram_dump_mchbar_registers();
#endif
/* This will not work if TSEG is in place! */
u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
- printk_debug("TOM: 0x%08x\n", tom);
+ printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom);
ram_check(0x00000000, 0x000a0000);
//ram_check(0x00100000, tom);
}
* memory completely, but that's a wonderful clean up task for another
* day.
*/
- if (resume_backup_memory)
- memcpy(resume_backup_memory, CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
+ if (resume_backup_memory)
+ memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
/* Magic for S3 resume */
pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
}
#endif
}
-
-#include "cpu/intel/model_106cx/cache_as_ram_disable.c"
projects / coreboot.git / blobdiff