Since some people disapprove of white space cleanups mixed in regular commits

[coreboot.git] / src / mainboard / intel / d945gclf / romstage.c

diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c
index 1441bb559720ca42f62f0b58bd104a0a201db3dc..45e9fb1341a1d52354923b57d1c387cc0ad333db 100644 (file)
--- a/src/mainboard/intel/d945gclf/romstage.c
+++ b/src/mainboard/intel/d945gclf/romstage.c
@@ -1,6 +1,6 @@
 /*
  * This file is part of the coreboot project.
- * 
+ *
  * Copyright (C) 2007-2008 coresystems GmbH
  *
  * This program is free software; you can redistribute it and/or
@@ -18,7 +18,6 @@
  */
 
 // __PRE_RAM__ means: use "unsigned" for device, not a struct.
-#define __PRE_RAM__
 
 /* Configuration of the i945 driver */
 #define CHIPSET_I945GC 1
@@ -39,7 +38,7 @@
 
 #include <console/console.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include <cpu/x86/bist.h>
 
 #if CONFIG_USBDEBUG_DIRECT
@@ -60,7 +59,7 @@
 static void setup_ich7_gpios(void)
 {
        /* TODO: This is highly board specific and should be moved */
-       printk_debug(" GPIOS...");
+       printk(BIOS_DEBUG, " GPIOS...");
        /* General Registers */
        outl(0x3f3df7c1, DEFAULT_GPIOBASE + 0x00);      /* GPIO_USE_SEL */
        outl(0xc6fcbfc3, DEFAULT_GPIOBASE + 0x04);      /* GP_IO_SEL */
@@ -83,7 +82,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "northbridge/intel/i945/raminit.h"
 #include "northbridge/intel/i945/raminit.c"
-#include "northbridge/intel/i945/reset_test.c"
 #include "northbridge/intel/i945/errata.c"
 #include "northbridge/intel/i945/debug.c"
 
@@ -99,7 +97,6 @@ static void ich7_enable_lpc(void)
        pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c0681);
 }
 
-
 /* This box has two superios, so enabling serial becomes slightly excessive.
  * We disable a lot of stuff to make sure that there are no conflicts between
  * the two. Also set up the GPIOs from the beginning. This is the "no schematic
@@ -108,7 +105,7 @@ static void ich7_enable_lpc(void)
 static void early_superio_config_lpc47m15x(void)
 {
        device_t dev;
-       
+
        dev=PNP_DEV(0x2e, LPC47M15X_SP1);
        pnp_enter_conf_state(dev);
 
@@ -216,8 +213,6 @@ static void early_ich7_init(void)
        RCBA32(0x2034) = reg32;
 }
 
-#include "southbridge/intel/i82801gx/cmos_failover.c"
-
 #include <cbmem.h>
 
 // Now, this needs to be included because it relies on the symbol
@@ -228,7 +223,7 @@ static void early_ich7_init(void)
 //
 #include "lib/cbmem.c"
 
-void real_main(unsigned long bist)
+void main(unsigned long bist)
 {
        u32 reg32;
        int boot_mode = 0;
@@ -254,7 +249,7 @@ void real_main(unsigned long bist)
        report_bist_failure(bist);
 
        if (MCHBAR16(SSKPD) == 0xCAFE) {
-               printk_debug("soft reset detected.\n");
+               printk(BIOS_DEBUG, "soft reset detected.\n");
                boot_mode = 1;
        }
 
@@ -265,23 +260,23 @@ void real_main(unsigned long bist)
 
         /* Read PM1_CNT */
        reg32 = inl(DEFAULT_PMBASE + 0x04);
-       printk_debug("PM1_CNT: %08x\n", reg32);
+       printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
        if (((reg32 >> 10) & 7) == 5) {
 #if CONFIG_HAVE_ACPI_RESUME
-               printk_debug("Resume from S3 detected.\n");
+               printk(BIOS_DEBUG, "Resume from S3 detected.\n");
                boot_mode = 2;
                /* Clear SLP_TYPE. This will break stage2 but
                 * we care for that when we get there.
                 */
                outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
 #else
-               printk_debug("Resume from S3 detected, but disabled.\n");
+               printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
 #endif
        }
 
        /* Enable SPD ROMs and DDR-II DRAM */
        enable_smbus();
-       
+
 #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
        dump_spd_registers();
 #endif
@@ -291,8 +286,8 @@ void real_main(unsigned long bist)
        /* Perform some initialization that must run before stage2 */
        early_ich7_init();
 
-       /* This should probably go away. Until now it is required 
-        * and mainboard specific 
+       /* This should probably go away. Until now it is required
+        * and mainboard specific
         */
        rcba_config();
 
@@ -312,7 +307,7 @@ void real_main(unsigned long bist)
                /* This will not work if TSEG is in place! */
                u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
 
-               printk_debug("TOM: 0x%08x\n", tom);
+               printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom);
                ram_check(0x00000000, 0x000a0000);
                //ram_check(0x00100000, tom);
        }
@@ -336,8 +331,8 @@ void real_main(unsigned long bist)
                 * memory completely, but that's a wonderful clean up task for another
                 * day.
                 */
-               if (resume_backup_memory) 
-                       memcpy(resume_backup_memory, CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
+               if (resume_backup_memory)
+                       memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
 
                /* Magic for S3 resume */
                pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
@@ -345,4 +340,3 @@ void real_main(unsigned long bist)
 #endif
 }
 
-#include "cpu/intel/model_106cx/cache_as_ram_disable.c"