mptable: Refactor mptable generation some more

[coreboot.git] / src / mainboard / intel / d945gclf / mptable.c

diff --git a/src/mainboard/intel/d945gclf/mptable.c b/src/mainboard/intel/d945gclf/mptable.c
index 2aff5e3d55f9ac90df3c3ffffee4e30e43530eb8..ab537cb71822c92c0d99eb70fcc780b92425ff60 100644 (file)
--- a/src/mainboard/intel/d945gclf/mptable.c
+++ b/src/mainboard/intel/d945gclf/mptable.c
@@ -32,7 +32,7 @@ static void *smp_write_config_table(void *v)
 
         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-       mptable_init(mc, "D945GCLF    ", LAPIC_ADDR);
+       mptable_init(mc, LAPIC_ADDR);
 
         smp_write_processors(mc);
 
@@ -76,21 +76,15 @@ static void *smp_write_config_table(void *v)
        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10);
 
        /* Local Ints:  Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
-       smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0);
-       smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1);
+       mptable_lintsrc(mc, isa_bus);
 
        /* Compute the checksums */
-       mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-       mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-
-       printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
-
-       return smp_next_mpe_entry(mc);
+       return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
 {
        void *v;
-       v = smp_write_floating_table(addr);
+       v = smp_write_floating_table(addr, 0);
        return (unsigned long)smp_write_config_table(v);
 }