Drop excessive whitespace randomly sprinkled in romstage.c files.

[coreboot.git] / src / mainboard / iei / pcisa-lx-800-r10 / romstage.c

diff --git a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
index e3351f12949f978b8c0182e5b675a56a46dcee2d..e889eed09ce27ad5853de455a59d61dcde72a506 100644 (file)
--- a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
+++ b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
@@ -30,13 +30,13 @@
 #include <cpu/amd/lxdef.h>
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
+#include <spd.h>
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 
+#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+
 static inline int spd_read_byte(unsigned int device, unsigned int address)
 {
        return smbus_read_byte(device, address);
@@ -50,9 +50,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 /* Hold Count - how long we will sit in reset */
 #define PLLMSRlo 0x00DE6000
 
-#define DIMM0 0xA0
-#define DIMM1 0xA2
-
 #include "northbridge/amd/lx/raminit.h"
 #include "northbridge/amd/lx/pll_reset.c"
 #include "northbridge/amd/lx/raminit.c"
@@ -71,7 +68,7 @@ void main(unsigned long bist)
        post_code(0x01);
 
        static const struct mem_controller memctrl[] = {
-               {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}
+               {.channel0 = {DIMM0, DIMM1}}
        };
 
        SystemPreInit();
@@ -101,4 +98,3 @@ void main(unsigned long bist)
        /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
        return;
 }
-