Simplify a few code chunks, fix whitespace and indentation.

[coreboot.git] / src / mainboard / iei / nova4899r / romstage.c

diff --git a/src/mainboard/iei/nova4899r/romstage.c b/src/mainboard/iei/nova4899r/romstage.c
index 69e2a28c386113b2151ef327fa2d650d0b54f169..0900f4ba3eef1e61ce7df632a593ae5e76fdfc55 100644 (file)
--- a/src/mainboard/iei/nova4899r/romstage.c
+++ b/src/mainboard/iei/nova4899r/romstage.c
@@ -18,17 +18,13 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "superio/winbond/w83977tf/w83977tf_early_serial.c"
 #include "southbridge/amd/cs5530/cs5530_enable_rom.c"
@@ -40,19 +36,11 @@
 
 static void main(unsigned long bist)
 {
-       /* Initialize the serial console. */
        w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
        uart_init();
        console_init();
-
-       /* Halt if there was a built in self test failure. */
        report_bist_failure(bist);
-
        cs5530_enable_rom();
-
-       /* Initialize RAM. */
        sdram_init();
-
-       /* Check RAM. */
        /* ram_check(0x00000000, 640 * 1024); */
 }