Drop excessive whitespace randomly sprinkled in romstage.c files.

[coreboot.git] / src / mainboard / ibm / e326 / romstage.c

diff --git a/src/mainboard/ibm/e326/romstage.c b/src/mainboard/ibm/e326/romstage.c
index 0b38ec78fa25c1547cbb7e97dd4b58fa97180141..f9a706d718c945f281f4bd29fc0f58772877b5d9 100644 (file)
--- a/src/mainboard/ibm/e326/romstage.c
+++ b/src/mainboard/ibm/e326/romstage.c
@@ -1,4 +1,3 @@
-
 #include <stdint.h>
 #include <string.h>
 #include <device/pci_def.h>
@@ -7,33 +6,26 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
-#include "lib/ramtest.c"
-
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/nsc/pc87366/pc87366_early_serial.c"
-
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
-
 #include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+#include <spd.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1)
 
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
-
 static void memreset_setup(void)
 {
        if (is_cpu_pre_c0()) {
@@ -67,28 +59,13 @@ static inline int spd_read_byte(unsigned device, unsigned address)
        return smbus_read_byte(device, address);
 }
 
-#define QRANK_DIMM_SUPPORT 1
-
 #include "northbridge/amd/amdk8/raminit.c"
 #include "resourcemap.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "lib/generic_sdram.c"
-
-#if CONFIG_LOGICAL_CPUS==1
-#define SET_NB_CFG_54 1
-#endif
 #include "cpu/amd/dualcore/dualcore.c"
-
-#define FIRST_CPU  1
-#define SECOND_CPU 1
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
-
-
-
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/model_fxx/init_cpus.c"
-
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
@@ -101,8 +78,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
                        .f1 = PCI_DEV(0, 0x18, 1),
                        .f2 = PCI_DEV(0, 0x18, 2),
                        .f3 = PCI_DEV(0, 0x18, 3),
-                       .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
-                       .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
+                       .channel0 = { DIMM0, DIMM2, 0, 0 },
+                       .channel1 = { DIMM1, DIMM3, 0, 0 },
                },
 #if CONFIG_MAX_PHYSICAL_CPUS > 1
                {
@@ -111,8 +88,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
                        .f1 = PCI_DEV(0, 0x19, 1),
                        .f2 = PCI_DEV(0, 0x19, 2),
                        .f3 = PCI_DEV(0, 0x19, 3),
-                       .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
-                       .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
+                       .channel0 = { DIMM4, DIMM6, 0, 0 },
+                       .channel1 = { DIMM5, DIMM7, 0, 0 },
                },
 #endif
        };
@@ -161,6 +138,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        sdram_initialize(ARRAY_SIZE(cpu), cpu);
 
        post_cache_as_ram();
-
 }
-