-#define ASSEMBLY 1
-#define __PRE_RAM__
-
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include "lib/ramtest.c"
-
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "superio/nsc/pc87366/pc87366_early_serial.c"
-
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
-
#include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+#include <spd.h>
#define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1)
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
-
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
- /* Set the memreset low */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
- /* Ensure the BIOS has control of the memory lines */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
+ /* Set the memreset low. */
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
+ /* Ensure the BIOS has control of the memory lines. */
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
} else {
- /* Ensure the CPU has controll of the memory lines */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
+ /* Ensure the CPU has control of the memory lines. */
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
}
}
{
if (is_cpu_pre_c0()) {
udelay(800);
- /* Set memreset_high */
- outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
+ /* Set memreset high. */
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
udelay(90);
}
}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
-#define QRANK_DIMM_SUPPORT 1
-
#include "northbridge/amd/amdk8/raminit.c"
#include "resourcemap.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
-
-#if CONFIG_LOGICAL_CPUS==1
-#define SET_NB_CFG_54 1
-#endif
#include "cpu/amd/dualcore/dualcore.c"
-
-#define FIRST_CPU 1
-#define SECOND_CPU 1
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
-
-#include "cpu/amd/car/copy_and_run.c"
-
#include "cpu/amd/car/post_cache_as_ram.c"
-
#include "cpu/amd/model_fxx/init_cpus.c"
-
-#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
.f1 = PCI_DEV(0, 0x18, 1),
.f2 = PCI_DEV(0, 0x18, 2),
.f3 = PCI_DEV(0, 0x18, 3),
- .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
- .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
+ .channel0 = { DIMM0, DIMM2, 0, 0 },
+ .channel1 = { DIMM1, DIMM3, 0, 0 },
},
#if CONFIG_MAX_PHYSICAL_CPUS > 1
{
.f1 = PCI_DEV(0, 0x19, 1),
.f2 = PCI_DEV(0, 0x19, 2),
.f3 = PCI_DEV(0, 0x19, 3),
- .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
- .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
+ .channel0 = { DIMM4, DIMM6, 0, 0 },
+ .channel1 = { DIMM5, DIMM7, 0, 0 },
},
#endif
};
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
-
- amd8111_enable_rom();
}
- if (bist == 0) {
+ if (bist == 0)
init_cpus(cpu_init_detectedx);
- }
pc87366_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
setup_ibm_e326_resource_map();
needs_reset = setup_coherent_ht_domain();
-
+
#if CONFIG_LOGICAL_CPUS==1
// It is said that we should start core1 after all core0 launched
start_other_cores();
needs_reset |= ht_setup_chains_x();
if (needs_reset) {
- print_info("ht reset -\r\n");
+ print_info("ht reset -\n");
soft_reset();
}
sdram_initialize(ARRAY_SIZE(cpu), cpu);
post_cache_as_ram();
-
}
projects / coreboot.git / blobdiff