This patch fixes the remaining stack protector problem on v2. The DISTRO_CFLAGS were...

[coreboot.git] / src / mainboard / ibm / e326 / Config.lb

diff --git a/src/mainboard/ibm/e326/Config.lb b/src/mainboard/ibm/e326/Config.lb
index 604a82d46dd4486b3a0b8d941bf607bbd0d3f8de..44137a263bd092f012827555e3cefa0957e7fb6a 100644 (file)
--- a/src/mainboard/ibm/e326/Config.lb
+++ b/src/mainboard/ibm/e326/Config.lb
@@ -1,6 +1,6 @@
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FALLBACK_IMAGE
        default ROM_SECTION_SIZE   = FALLBACK_SIZE
@@ -12,18 +12,18 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
-default _ROMBASE      = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
+default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -45,7 +45,28 @@ arch i386 end
 driver mainboard.o
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
+#object reset.o
 
+if USE_DCACHE_RAM
+
+if CONFIG_USE_INIT
+
+makerule ./auto.o
+        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+        action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o" 
+end
+
+else    
+                
+makerule ./auto.inc
+        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+        action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"         
+        action "perl -e 's/.rodata/.rom.data/g' -pi $@"
+        action "perl -e 's/.text/.section .rom.text/g' -pi $@"
+end
+
+end
+else
 ##
 ## Romcc output
 ##
@@ -68,16 +89,30 @@ makerule ./auto.inc
        action  "./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 
+end
+
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
-mainboardinit cpu/x86/16bit/entry16.inc
+if USE_FALLBACK_IMAGE
+        mainboardinit cpu/x86/16bit/entry16.inc
+        ldscript /cpu/x86/16bit/entry16.lds
+end
+
 mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
+
+if USE_DCACHE_RAM
+        if CONFIG_USE_INIT
+                ldscript /cpu/x86/32bit/entry32.lds
+        end
+
+        if CONFIG_USE_INIT
+                ldscript      /cpu/amd/car/cache_as_ram.lds
+        end
+end
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if USE_FALLBACK_IMAGE 
        mainboardinit cpu/x86/16bit/reset16.inc 
@@ -87,8 +122,11 @@ else
        ldscript /cpu/x86/32bit/reset32.lds 
 end
 
+if USE_DCACHE_RAM
+else
 ### Should this be in the northbridge code?
 mainboardinit arch/i386/lib/cpu_reset.inc
+end
 
 ##
 ## Include an id string (For safe flashing)
@@ -96,20 +134,44 @@ mainboardinit arch/i386/lib/cpu_reset.inc
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
+if USE_DCACHE_RAM
+##
+## Setup Cache-As-Ram
+##
+mainboardinit cpu/amd/car/cache_as_ram.inc
+end
+
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
 if USE_FALLBACK_IMAGE
-       ldscript /arch/i386/lib/failover.lds 
-       mainboardinit ./failover.inc
+if USE_DCACHE_RAM
+       ldscript /arch/i386/lib/failover.lds
+else
+       ldscript /arch/i386/lib/failover.lds
+        mainboardinit ./failover.inc
+end
 end
 
 ###
 ### O.k. We aren't just an intermediary anymore!
 ###
 
+##
+## Setup RAM
+##
+if USE_DCACHE_RAM
+
+if CONFIG_USE_INIT
+initobject auto.o
+else
+mainboardinit ./auto.inc
+end
+
+else
+
 ##
 ## Setup RAM
 ##
@@ -119,15 +181,21 @@ mainboardinit cpu/x86/sse/enable_sse.inc
 mainboardinit ./auto.inc
 mainboardinit cpu/x86/sse/disable_sse.inc
 mainboardinit cpu/x86/mmx/disable_mmx.inc
+end
 
 ##
 ## Include the secondary Configuration files 
 ##
-dir /pc80
 config chip.h
 
 
 chip northbridge/amd/amdk8/root_complex
+       device apic_cluster 0 on
+               chip cpu/amd/socket_940
+                       device apic 0 on end
+               end
+       end
+
        device pci_domain 0 on
                chip northbridge/amd/amdk8
                        device pci 18.0 on end # LDT 0
@@ -144,9 +212,13 @@ chip northbridge/amd/amdk8/root_complex
                                                device pci 0.1 on end
                                                device pci 0.2 on end
                                                device pci 1.0 off end
+                                                chip drivers/pci/onboard
+                                                        device pci 5.0 on end # ATI Rage XL
+                                                        register "rom_address" = "0xfff80000"
+                                                end
                                        end
                                        device pci 1.0 on
-                                               chip superio/NSC/pc87366
+                                               chip superio/nsc/pc87366
                                                        device  pnp 2e.0 off  # Floppy 
                                                                 io 0x60 = 0x3f0
                                                                irq 0x70 = 6
@@ -182,6 +254,8 @@ chip northbridge/amd/amdk8/root_complex
                                        device pci 1.3 on end
                                        device pci 1.5 off end
                                        device pci 1.6 off end
+                                       register "ide0_enable" = "1"
+                                       register "ide1_enable" = "1"
                                end
                        end #  device pci 18.0 
                        device pci 18.0 on end # LDT2
@@ -189,22 +263,6 @@ chip northbridge/amd/amdk8/root_complex
                        device pci 18.2 on end
                        device pci 18.3 on end
                end
-               chip northbridge/amd/amdk8
-                       device pci 19.0 on end
-                       device pci 19.0 on end
-                       device pci 19.0 on end
-                       device pci 19.1 on end
-                       device pci 19.2 on end
-                       device pci 19.3 on end
-               end
        end 
-       device apic_cluster 0 on
-               chip cpu/amd/socket_940
-                       device apic 0 on end
-               end
-               chip cpu/amd/socket_940
-                       device apic 1 on end
-               end
-       end
 end