Move "select CACHE_AS_RAM" lines from boards into CPU socket.

[coreboot.git] / src / mainboard / hp / dl165_g6_fam10 / Kconfig

diff --git a/src/mainboard/hp/dl165_g6_fam10/Kconfig b/src/mainboard/hp/dl165_g6_fam10/Kconfig
index 7052f5bc8e0ca50a673dd20a4e8a2f365775f00a..e20420df09ffcbf640fe49194d560974180831ea 100644 (file)
--- a/src/mainboard/hp/dl165_g6_fam10/Kconfig
+++ b/src/mainboard/hp/dl165_g6_fam10/Kconfig
@@ -9,17 +9,20 @@ config BOARD_SPECIFIC_OPTIONS # dummy
        select SOUTHBRIDGE_BROADCOM_BCM21000
        select SOUTHBRIDGE_BROADCOM_BCM5785
        select SUPERIO_NSC_PC87417
+       select DIMM_DDR2
+       select DIMM_REGISTERED
        select HAVE_OPTION_TABLE
        select HAVE_BUS_CONFIG
        select HAVE_PIRQ_TABLE
        select HAVE_MP_TABLE
-       select CACHE_AS_RAM
        select HAVE_HARD_RESET
        select LIFT_BSP_APIC_ID
        select BOARD_ROMSIZE_KB_1024
+       select RAMINIT_SYSINFO
        select ENABLE_APIC_EXT_ID
        select AMDMCT
        select TINY_BOOTBLOCK
+       select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
        string
@@ -49,10 +52,6 @@ config MAINBOARD_PART_NUMBER
        string
        default "ProLiant DL165 G6 (Fam10)"
 
-config HW_MEM_HOLE_SIZEK
-       hex
-       default 0x100000
-
 config MAX_CPUS
        int
        default 12