Broadcom BCM5785: Add TINY_BOOTBLOCK support.

[coreboot.git] / src / mainboard / hp / dl145_g3 / romstage.c

diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c
index d2e393cbe137759cf0099010c2c454990b19d468..eeac3e5b6a7bbce59543b2aaf9b7b5cd3164c899 100644 (file)
--- a/src/mainboard/hp/dl145_g3/romstage.c
+++ b/src/mainboard/hp/dl145_g3/romstage.c
@@ -38,40 +38,27 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
-
 #include <console/console.h>
-
 #include <cpu/amd/model_fxx_rev.h>
-
 #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
-#include "southbridge/broadcom/bcm5785/bcm5785_enable_rom.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
-
 #include "superio/serverengines/pilot/pilot_early_serial.c"
 #include "superio/serverengines/pilot/pilot_early_init.c"
 #include "superio/nsc/pc87417/pc87417_early_serial.c"
-
 #include "cpu/x86/bist.h"
-
 #include "northbridge/amd/amdk8/debug.c"
-
 #include "cpu/x86/mtrr/earlymtrr.c"
-
 #include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1)
 #define RTC_DEV PNP_DEV(0x4e, PC87417_RTC)
 
-#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
 
 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 {
@@ -93,15 +80,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdk8/raminit_f.c"
 #include "lib/generic_sdram.c"
 #include <spd.h>
-
 #include "cpu/amd/dualcore/dualcore.c"
-
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/model_fxx/init_cpus.c"
-
 #include "cpu/amd/model_fxx/fidvid.c"
-
 #include "northbridge/amd/amdk8/early_ht.c"
 
 #if 0
@@ -146,9 +128,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
        static const uint16_t spd_addr[] = {
                // first node
-                DIMM0, DIMM2, 0, 0,
-                DIMM1, DIMM3, 0, 0,
-
+               DIMM0, DIMM2, 0, 0,
+               DIMM1, DIMM3, 0, 0,
                // second node
                DIMM4, DIMM6, 0, 0,
                DIMM5, DIMM7, 0, 0,
@@ -156,24 +137,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
        struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
                + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-
        int needs_reset;
        unsigned bsp_apicid = 0;
 
        if (!cpu_init_detectedx && boot_cpu()) {
                /* Nothing special needs to be done to find bus 0 */
                /* Allow the HT devices to be found */
-
                enumerate_ht_chain();
-               bcm5785_enable_rom();
                bcm5785_enable_lpc();
-               //enable RTC
-               pc87417_enable_dev(RTC_DEV);
+               pc87417_enable_dev(RTC_DEV); /* Enable RTC */
        }
 
-       if (bist == 0) {
+       if (bist == 0)
                bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-       }
 
        pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 
@@ -248,4 +224,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
        post_cache_as_ram();
 }
-