remove usbdebug.h include from mainboard/romstage code

[coreboot.git] / src / mainboard / gigabyte / ma785gmt / romstage.c

diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c
index f0585dbbb0eafbff05c01ec726bc8dcb50e2fba7..4572169b87a9b8163d952d23c81045668fd60c0a 100644 (file)
--- a/src/mainboard/gigabyte/ma785gmt/romstage.c
+++ b/src/mainboard/gigabyte/ma785gmt/romstage.c
@@ -39,19 +39,19 @@
 #include <console/loglevel.h>
 #include "cpu/x86/bist.h"
 #include "superio/ite/it8718f/early_serial.c"
-#include <usbdebug.h>
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
 #include "southbridge/amd/rs780/early_setup.c"
-#include "southbridge/amd/sb700/early_setup.c"
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
 #include "northbridge/amd/amdfam10/debug.c"
 
 static void activate_spd_rom(const struct mem_controller *ctrl) { }
 
 static int spd_read_byte(u32 device, u32 address)
 {
-       return smbus_read_byte(device, address);
+       return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
 }
 
 #include "northbridge/amd/amdfam10/amdfam10.h"
@@ -100,10 +100,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
        it8718f_enable_serial(0, CONFIG_TTYS0_BASE);
        it8718f_disable_reboot();
-       uart_init();
-
        console_init();
-       printk(BIOS_DEBUG, "\n");
 
 //     dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);