Please bear with me - another rename checkin. This qualifies as trivial, no

[coreboot.git] / src / mainboard / gigabyte / m57sli / cache_as_ram_auto.c

diff --git a/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c b/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c
index c39f626d28de2b3bb2be9892682fa197e66c5243..fb52c86c245056cf4969accc957626c6239cb5db 100644 (file)
--- a/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c
+++ b/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c
@@ -1,5 +1,5 @@
 /*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
  *
  * Copyright (C) 2007 AMD
  * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
@@ -93,6 +93,7 @@
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
+#define GPIO_DEV PNP_DEV(0x2e, IT8716F_GPIO)
 
 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
 
@@ -134,10 +135,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #define MCP55_PCI_E_X_0 0
 
 #define MCP55_MB_SETUP \
-        RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \
-        RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \
-        RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \
-        RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \
+        RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x68,/* GPIO38 PCI_REQ3 */ \
+        RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x68,/* GPIO39 PCI_GNT3 */ \
+        RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x68,/* GPIO40 PCI_GNT2 */ \
+        RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x68,/* GPIO41 PCI_REQ2 */ \
         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
 
@@ -265,13 +266,27 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
         int needs_reset = 0;
         unsigned bsp_apicid = 0;
+       uint8_t tmp = 0;
 
         if (bist == 0) {
                bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
         }
 
        pnp_enter_ext_func_mode(SERIAL_DEV);
-        pnp_write_config(SERIAL_DEV, 0x23, 1);
+       /* The following line will set CLKIN to 24 MHz, external */
+       pnp_write_config(SERIAL_DEV, IT8716F_CONFIG_REG_CLOCKSEL, 0x11);
+       tmp = pnp_read_config(SERIAL_DEV, IT8716F_CONFIG_REG_SWSUSP);
+       /* Is serial flash enabled? Then enable writing to serial flash. */
+       if (tmp & 0x0e) {
+               pnp_write_config(SERIAL_DEV, IT8716F_CONFIG_REG_SWSUSP, tmp | 0x10);
+               pnp_set_logical_device(GPIO_DEV);
+               /* Set Serial Flash interface to 0x0820 */
+               pnp_write_config(GPIO_DEV, 0x64, 0x08);
+               pnp_write_config(GPIO_DEV, 0x65, 0x20);
+               /* We can get away with not resetting the logical device because
+                * it8716f_enable_dev(SERIAL_DEV, TTYS0_BASE) will do that.
+                */
+       }
        it8716f_enable_dev(SERIAL_DEV, TTYS0_BASE);
        pnp_exit_ext_func_mode(SERIAL_DEV);