Please bear with me - another rename checkin. This qualifies as trivial, no

[coreboot.git] / src / mainboard / gigabyte / m57sli / cache_as_ram_auto.c

diff --git a/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c b/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c
index 30e2e69acedfa4bd2b6175eefb90669e10605daf..fb52c86c245056cf4969accc957626c6239cb5db 100644 (file)
--- a/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c
+++ b/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c
@@ -1,5 +1,5 @@
 /*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
  *
  * Copyright (C) 2007 AMD
  * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
@@ -273,8 +273,8 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
         }
 
        pnp_enter_ext_func_mode(SERIAL_DEV);
-       /* The following line will set CLKIN to 24 MHz */
-       pnp_write_config(SERIAL_DEV, IT8716F_CONFIG_REG_CLOCKSEL, 1);
+       /* The following line will set CLKIN to 24 MHz, external */
+       pnp_write_config(SERIAL_DEV, IT8716F_CONFIG_REG_CLOCKSEL, 0x11);
        tmp = pnp_read_config(SERIAL_DEV, IT8716F_CONFIG_REG_SWSUSP);
        /* Is serial flash enabled? Then enable writing to serial flash. */
        if (tmp & 0x0e) {