fix further build.h dependencies that were undetected before we enabled it on

[coreboot.git] / src / mainboard / gigabyte / m57sli / cache_as_ram_auto.c

diff --git a/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c b/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c
index fb52c86c245056cf4969accc957626c6239cb5db..ecc7827428a652a0de5d0bdb9f1cef194c6db884 100644 (file)
--- a/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c
+++ b/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c
@@ -20,13 +20,11 @@
  */
 
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
 
 #define RAMINIT_SYSINFO 1
 
 #define K8_ALLOCATE_IO_RANGE 1
-//#define K8_SCAN_PCI_BUS 1
-
 
 #define QRANK_DIMM_SUPPORT 1
 
@@ -39,13 +37,14 @@
 //if we want to wait for core1 done before DQS training, set it to 0
 #define K8_SET_FIDVID_CORE0_ONLY 1
 
-#if K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
 #endif
 
 #define DBGP_DEFAULT 7
  
 #include <stdint.h>
+#include <string.h>
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
 #include <arch/io.h>
@@ -55,14 +54,14 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#if USE_FAILOVER_IMAGE==0
+#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #if CONFIG_USBDEBUG_DIRECT
 #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c"
 #include "pc80/usbdebug_direct_serial.c"
 #endif
-#include "ram/ramtest.c"
+#include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>
 
@@ -78,14 +77,10 @@
 #include "superio/ite/it8716f/it8716f_early_serial.c"
 #include "superio/ite/it8716f/it8716f_early_init.c"
 
-#if USE_FAILOVER_IMAGE==0
+#if CONFIG_USE_FAILOVER_IMAGE==0
 
 #include "cpu/x86/bist.h"
 
-#if CONFIG_USE_INIT == 0
-        #include "lib/memcpy.c"
-#endif
-
 #include "northbridge/amd/amdk8/debug.c"
 
 #include "cpu/amd/mtrr/amd_earlymtrr.c"
@@ -122,7 +117,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "northbridge/amd/amdk8/raminit_f.c"
 
-#include "sdram/generic_sdram.c"
+#include "lib/generic_sdram.c"
 
 #include "resourcemap.c" 
 
@@ -155,7 +150,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #endif
 
-#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1))
+#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
 
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
@@ -222,7 +217,7 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
                 );
 
  fallback_image:
-#if HAVE_FAILOVER_BOOT==1
+#if CONFIG_HAVE_FAILOVER_BOOT==1
         __asm__ volatile ("jmp __fallback_image"
                 : /* outputs */
                 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
@@ -235,21 +230,21 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-#if HAVE_FAILOVER_BOOT==1 
-    #if USE_FAILOVER_IMAGE==1
+#if CONFIG_HAVE_FAILOVER_BOOT==1 
+    #if CONFIG_USE_FAILOVER_IMAGE==1
        failover_process(bist, cpu_init_detectedx);     
     #else
        real_main(bist, cpu_init_detectedx);
     #endif
 #else
-    #if USE_FALLBACK_IMAGE == 1
+    #if CONFIG_USE_FALLBACK_IMAGE == 1
        failover_process(bist, cpu_init_detectedx);     
     #endif
        real_main(bist, cpu_init_detectedx);
 #endif
 }
 
-#if USE_FAILOVER_IMAGE==0
+#if CONFIG_USE_FAILOVER_IMAGE==0
 
 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
@@ -262,7 +257,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 #endif
        };
 
-        struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
+        struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 
         int needs_reset = 0;
         unsigned bsp_apicid = 0;
@@ -284,10 +279,10 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
                pnp_write_config(GPIO_DEV, 0x64, 0x08);
                pnp_write_config(GPIO_DEV, 0x65, 0x20);
                /* We can get away with not resetting the logical device because
-                * it8716f_enable_dev(SERIAL_DEV, TTYS0_BASE) will do that.
+                * it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE) will do that.
                 */
        }
-       it8716f_enable_dev(SERIAL_DEV, TTYS0_BASE);
+       it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
        pnp_exit_ext_func_mode(SERIAL_DEV);
 
         setup_mb_resource_map();
@@ -307,7 +302,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
         print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
 
-#if MEM_TRAIN_SEQ == 1
+#if CONFIG_MEM_TRAIN_SEQ == 1
         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
 #endif
         setup_coherent_ht_domain(); // routing table and start other core0