Move "select CACHE_AS_RAM" lines from boards into CPU socket.

[coreboot.git] / src / mainboard / gigabyte / m57sli / Kconfig

diff --git a/src/mainboard/gigabyte/m57sli/Kconfig b/src/mainboard/gigabyte/m57sli/Kconfig
index e0e582e25351fc0da135ae88c1ae6d0367f74de0..e36dccc8da40cacfe927ee0917d2975ba1f308d0 100644 (file)
--- a/src/mainboard/gigabyte/m57sli/Kconfig
+++ b/src/mainboard/gigabyte/m57sli/Kconfig
@@ -4,21 +4,27 @@ config BOARD_SPECIFIC_OPTIONS # dummy
        def_bool y
        select ARCH_X86
        select CPU_AMD_SOCKET_AM2
+       select DIMM_DDR2
        select NORTHBRIDGE_AMD_AMDK8
        select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
        select SOUTHBRIDGE_NVIDIA_MCP55
+       select MCP55_USE_NIC
+       select MCP55_USE_AZA
        select SUPERIO_ITE_IT8716F
        select SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL
        select HAVE_BUS_CONFIG
        select HAVE_OPTION_TABLE
        select HAVE_PIRQ_TABLE
        select HAVE_MP_TABLE
-       select CACHE_AS_RAM
        select HAVE_HARD_RESET
        select LIFT_BSP_APIC_ID
        select HAVE_ACPI_TABLES
        select K8_REV_F_SUPPORT
        select BOARD_ROMSIZE_KB_512
+       select RAMINIT_SYSINFO
+       select QRANK_DIMM_SUPPORT
+       select K8_ALLOCATE_IO_RANGE
+       select SET_FIDVID
 
 config MAINBOARD_DIR
        string
@@ -56,10 +62,6 @@ config PCI_64BIT_PREF_MEM
        bool
        default n
 
-config HW_MEM_HOLE_SIZEK
-       hex
-       default 0x100000
-
 config MAX_CPUS
        int
        default 2
@@ -68,10 +70,6 @@ config MAX_PHYSICAL_CPUS
        int
        default 1
 
-config HW_MEM_HOLE_SIZE_AUTO_INC
-       bool
-       default n
-
 config HT_CHAIN_UNITID_BASE
        hex
        default 0x0
@@ -96,4 +94,8 @@ config IRQ_SLOT_COUNT
        int
        default 11
 
+config MCP55_PCI_E_X_0
+       int
+       default 0
+
 endif # BOARD_GIGABYTE_M57SLI