Move "select CACHE_AS_RAM" lines from boards into CPU socket.

[coreboot.git] / src / mainboard / gigabyte / m57sli / Kconfig

diff --git a/src/mainboard/gigabyte/m57sli/Kconfig b/src/mainboard/gigabyte/m57sli/Kconfig
index 19855671d6d037662ce36a3d3a5adb952b3bf5f0..e36dccc8da40cacfe927ee0917d2975ba1f308d0 100644 (file)
--- a/src/mainboard/gigabyte/m57sli/Kconfig
+++ b/src/mainboard/gigabyte/m57sli/Kconfig
@@ -16,7 +16,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
        select HAVE_OPTION_TABLE
        select HAVE_PIRQ_TABLE
        select HAVE_MP_TABLE
-       select CACHE_AS_RAM
        select HAVE_HARD_RESET
        select LIFT_BSP_APIC_ID
        select HAVE_ACPI_TABLES
@@ -24,6 +23,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
        select BOARD_ROMSIZE_KB_512
        select RAMINIT_SYSINFO
        select QRANK_DIMM_SUPPORT
+       select K8_ALLOCATE_IO_RANGE
+       select SET_FIDVID
 
 config MAINBOARD_DIR
        string
@@ -93,4 +94,8 @@ config IRQ_SLOT_COUNT
        int
        default 11
 
+config MCP55_PCI_E_X_0
+       int
+       default 0
+
 endif # BOARD_GIGABYTE_M57SLI