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Fix all warnings in the tree
[coreboot.git] / src / mainboard / gigabyte / ga_2761gxdk / romstage.c
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
index 915122f8796c405af1480b8117381a7dee597d0f..e4762bfd092a766fc494a884e833332f274c22e1 100644 (file)
--- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
@@ -21,9 +21,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #define RAMINIT_SYSINFO 1
 
 #define K8_ALLOCATE_IO_RANGE 1
@@ -35,9 +32,9 @@
 #endif
 
 //used by init_cpus and fidvid
-#define K8_SET_FIDVID 1
+#define SET_FIDVID 1
 //if we want to wait for core1 done before DQS training, set it to 0
-#define K8_SET_FIDVID_CORE0_ONLY 1
+#define SET_FIDVID_CORE0_ONLY 1
 
 #if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
@@ -53,14 +50,12 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#if CONFIG_USBDEBUG_DIRECT
-#include "southbridge/sis/sis966/sis966_enable_usbdebug_direct.c"
-#include "pc80/usbdebug_direct_serial.c"
+#include <pc80/mc146818rtc.h>
+
+#include <console/console.h>
+#if CONFIG_USBDEBUG
+#include "southbridge/sis/sis966/sis966_enable_usbdebug.c"
+#include "pc80/usbdebug_serial.c"
 #endif
 #include "lib/ramtest.c"
 
@@ -81,7 +76,7 @@
 
 #include "northbridge/amd/amdk8/debug.c"
 
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 
@@ -89,10 +84,6 @@
 
 #include "southbridge/sis/sis966/sis966_early_ctrl.c"
 
-static void memreset_setup(void)
-{
-}
-
 static void memreset(int controllers, const struct mem_controller *ctrl)
 {
 }
@@ -108,12 +99,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 }
 
 #include "northbridge/amd/amdk8/amdk8_f.h"
-#include "northbridge/amd/amdk8/coherent_ht.c"
-
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-
+#include "northbridge/amd/amdk8/coherent_ht.c"
 #include "northbridge/amd/amdk8/raminit_f.c"
-
 #include "lib/generic_sdram.c"
 
 #include "resourcemap.c"
@@ -135,9 +123,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
 
 #include "southbridge/sis/sis966/sis966_early_setup_ss.h"
-#include "southbridge/sis/sis966/sis966_early_setup_car.c"
-
-#include "cpu/amd/car/copy_and_run.c"
 
 #include "cpu/amd/car/post_cache_as_ram.c"
 
@@ -147,11 +132,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "northbridge/amd/amdk8/early_ht.c"
 
-
 static void sio_setup(void)
 {
-
-        unsigned value;
         uint32_t dword;
         uint8_t byte;
 
@@ -171,15 +153,16 @@ static void sio_setup(void)
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
        static const uint16_t spd_addr [] = {
+                       // Node 0
                        (0xa<<3)|0, (0xa<<3)|2, 0, 0,
                        (0xa<<3)|1, (0xa<<3)|3, 0, 0,
-#if CONFIG_MAX_PHYSICAL_CPUS > 1
+                       // Node 1
                        (0xa<<3)|4, (0xa<<3)|6, 0, 0,
                        (0xa<<3)|5, (0xa<<3)|7, 0, 0,
-#endif
        };
 
-        struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+        struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE +
+               CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 
         int needs_reset = 0;
         unsigned bsp_apicid = 0;
@@ -212,15 +195,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        /* Halt if there was a built in self test failure */
        report_bist_failure(bist);
 
-
-#if CONFIG_USBDEBUG_DIRECT
-       sis966_enable_usbdebug_direct(DBGP_DEFAULT);
-       early_usbdebug_direct_init();
+#if CONFIG_USBDEBUG
+       sis966_enable_usbdebug(DBGP_DEFAULT);
+       early_usbdebug_init();
 #endif
         console_init();
        printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 
-        print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
+        print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 
 #if CONFIG_MEM_TRAIN_SEQ == 1
         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
@@ -241,12 +223,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         /* it will set up chains and store link pair for optimization later */
         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 
-#if K8_SET_FIDVID == 1
+#if SET_FIDVID == 1
 
         {
                 msr_t msr;
                 msr=rdmsr(0xc0010042);
-                print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+                print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 
         }
 
@@ -260,7 +242,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         {
                 msr_t msr;
                 msr=rdmsr(0xc0010042);
-                print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+                print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 
         }
 #endif
@@ -270,7 +252,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
         // fidvid change will issue one LDTSTOP and the HT change will be effective too
         if (needs_reset) {
-                print_info("ht reset -\r\n");
+                print_info("ht reset -\n");
                soft_reset();
         }
         allow_all_aps_stop(bsp_apicid);
@@ -281,8 +263,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         sis_init_stage1();
         enable_smbus();
 
-        memreset_setup();
-
         //do we need apci timer, tsc...., only debug need it for better output
         /* all ap stopped? */
 //        init_timer(); // Need to use TMICT to synconize FID/VID
my coreboot WIP stuff (asus m5a99x-evo board)