* Explicitly add __PRE_RAM__ where it should be added.

[coreboot.git] / src / mainboard / gigabyte / ga-6bxc / auto.c

diff --git a/src/mainboard/gigabyte/ga-6bxc/auto.c b/src/mainboard/gigabyte/ga-6bxc/auto.c
index e67431afc513f4cbc9e79c0685f63e755fc359a0..1b440a759e8b992e403043fb9ce2ef12df5d3dbf 100644 (file)
--- a/src/mainboard/gigabyte/ga-6bxc/auto.c
+++ b/src/mainboard/gigabyte/ga-6bxc/auto.c
@@ -19,6 +19,7 @@
  */
 
 #define ASSEMBLY 1
+#define __PRE_RAM__
 
 #include <stdint.h>
 #include <device/pci_def.h>
@@ -29,7 +30,8 @@
 #include <stdlib.h>
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
-#include "ram/ramtest.c"
+#include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -54,10 +56,14 @@ static void main(unsigned long bist)
        if (bist == 0)
                early_mtrr_init();
 
-       it8671f_enable_serial(SERIAL_DEV, TTYS0_BASE);
+       it8671f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
        uart_init();
        console_init();
        report_bist_failure(bist);
+
+       /* Enable access to the full ROM chip, needed very early by CBFS. */
+       i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
+
        enable_smbus();
        /* dump_spd_registers(); */
        sdram_set_registers();