+## we don't use CONFIG_USE_DCACHE_RAM by default
+default CONFIG_USE_DCACHE_RAM=0
##
## Compute the location and size of where this firmware image
## (coreboot plus bootloader) will live in the boot rom chip.
##
-default ROM_SIZE = 256 * 1024
-default ROM_SECTION_SIZE = ROM_SIZE
-default ROM_SECTION_OFFSET = 0
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+default CONFIG_ROM_SIZE = 256 * 1024
+default CONFIG_ROM_SECTION_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_ROM_SECTION_OFFSET = CONFIG_ROM_SIZE - CONFIG_ROM_SECTION_SIZE
##
## Compute where this copy of coreboot will start in the boot rom
##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
+default CONFIG_ROMBASE = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1)
##
## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+## CONFIG_XIP_ROM_BASE must be a multiple of CONFIG_XIP_ROM_SIZE
##
-default XIP_ROM_SIZE=32*1024
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+default CONFIG_XIP_ROM_SIZE=32*1024
+default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - CONFIG_XIP_ROM_SIZE )
##
## Set all of the defaults for an x86 architecture
##
driver mainboard.o
-if HAVE_PIRQ_TABLE object irq_tables.o end
+if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o
-##
-## Romcc output
-##
-makerule ./failover.E
- depends "$(MAINBOARD)/failover.c ../romcc"
- action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./failover.inc
- depends "$(MAINBOARD)/failover.c ../romcc"
- action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E
- depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
- depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-mainboardinit cpu/x86/16bit/reset16.inc
-ldscript /cpu/x86/16bit/reset16.lds
-
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
+## ALL dependencies for CONFIG_USE_DCACHE_RAM go here.
+## That way, later, we can simply yank them if we wish.
+## We include the old-fashioned entry code in the ! CONFIG_USE_DCACHE_RAM case.
+## we do not use failover yet in this case. This is a work in progress.
+if CONFIG_USE_DCACHE_RAM
+ ##
+ ##
+ mainboardinit arch/i386/init/entry.S
+ mainboardinit arch/i386/init/car.S
+ ldscript /arch/i386/init/ldscript.ld
+
+ ## The main code for the rom section is called rom.c
+ initobject rom.o
+else
+ ##
+ ## Romcc output
+ ##
+ makerule ./failover.E
+ depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
+ action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
+ end
+
+ makerule ./failover.inc
+ depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
+ action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
+ end
+
+ makerule ./auto.E
+ depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+ action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
+ end
+ makerule ./auto.inc
+ depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+ action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
+ end
+
+ ##
+ ## Build our 16 bit and 32 bit coreboot entry code
+ ##
+ mainboardinit cpu/x86/16bit/entry16.inc
+ mainboardinit cpu/x86/32bit/entry32.inc
+ ldscript /cpu/x86/16bit/entry16.lds
+ ldscript /cpu/x86/32bit/entry32.lds
+
+ ##
+ ## Build our reset vector (This is where coreboot is entered)
+ ##
+ mainboardinit cpu/x86/16bit/reset16.inc
+ ldscript /cpu/x86/16bit/reset16.lds
+
+ ### Should this be in the northbridge code?
+ mainboardinit arch/i386/lib/cpu_reset.inc
+
+ ##
+ ## Setup RAM
+ ##
+ mainboardinit cpu/x86/fpu/enable_fpu.inc
+ mainboardinit ./auto.inc
+
+ ## the id string will be in cbfs. We will expect flashrom to parse cbfs for the idstring in future.
+ ##
+ ## Include an id string (For safe flashing)
+ ##
+ mainboardinit arch/i386/lib/id.inc
+ ldscript /arch/i386/lib/id.lds
+
+##
+## end of CONFIG_USE_DCACHE_RAM bits.
##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu/enable_fpu.inc
-mainboardinit ./auto.inc
+end
##
## Include the secondary Configuration files
projects / coreboot.git / blobdiff