- First pass at getting the powerpc ports to compile

[coreboot.git] / src / mainboard / embeddedplanet / ep405pc / Config.lb

diff --git a/src/mainboard/embeddedplanet/ep405pc/Config.lb b/src/mainboard/embeddedplanet/ep405pc/Config.lb
index 5b9669b8fc003350cce6713ece39c18240e7ac08..9f071bf621baeb9ef8b197219cdb2844db905acb 100644 (file)
--- a/src/mainboard/embeddedplanet/ep405pc/Config.lb
+++ b/src/mainboard/embeddedplanet/ep405pc/Config.lb
@@ -2,21 +2,6 @@
 ## Config file for the Embedded Planet EP405PC Computing Engine
 ##
 
-uses PCIC0_CFGADDR 
-uses PCIC0_CFGDATA 
-uses UART0_IO_BASE
-
-##
-## Set PCI registers
-##
-default PCIC0_CFGADDR=0xeec00000
-default PCIC0_CFGDATA=0xeec00004
-
-##
-## Set UART base address
-##
-default UART0_IO_BASE=0xef600300
-
 ##
 ## Early board initialization, called from ppc_main()
 ##
@@ -24,12 +9,12 @@ initobject init.c
 driver pci_bridge.c
 
 arch ppc end
-cpu ppc/ppc4xx end
+chip cpu/ppc/ppc4xx device pnp 0.0 on end end
 
 ##
 ## Include the secondary Configuration files 
 ##
-southbridge winbond/w83c553 end
+chip southbridge/winbond/w83c553 device pnp 0.0 on end end
 
 ##
 ## Build the objects we have code for in this directory.