Simplify a few code chunks, fix whitespace and indentation.
[coreboot.git] / src / mainboard / digitallogic / msm800sev / romstage.c
index 0a9b6dfe98b5a2daf69334bc17a141c424fc06b1..14f04941f79104300f6bbeae1495ef3f99268862 100644 (file)
@@ -1,33 +1,32 @@
 #include <stdint.h>
+#include <stdlib.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
 #include <cpu/amd/lxdef.h>
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
+#include <spd.h>
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 
+#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
-               return smbus_read_byte(device, address);
+       return smbus_read_byte(device, address);
 }
 
 #define ManualConf 0           /* Do automatic strapped PLL config */
 #define PLLMSRhi 0x00001490 /* manual settings for the PLL */
 #define PLLMSRlo 0x02000030
-#define DIMM0 0xA0
-#define DIMM1 0xA2
+
 #include "northbridge/amd/lx/raminit.h"
 #include "northbridge/amd/lx/pll_reset.c"
 #include "northbridge/amd/lx/raminit.c"
@@ -36,17 +35,12 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "cpu/amd/model_lx/syspreinit.c"
 #include "cpu/amd/model_lx/msrinit.c"
 
-static void mb_gpio_init(void)
-{
-       /* Early mainboard specific GPIO setup */
-}
-
 void main(unsigned long bist)
 {
        post_code(0x01);
 
        static const struct mem_controller memctrl [] = {
-               {.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
+               {.channel0 = {DIMM0, DIMM1}}
        };
 
        SystemPreInit();
@@ -60,7 +54,6 @@ void main(unsigned long bist)
         */
        cs5536_disable_internal_uart();
        w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-       mb_gpio_init();
        uart_init();
        console_init();
 
@@ -69,7 +62,7 @@ void main(unsigned long bist)
 
        pll_reset(ManualConf);
 
-       cpuRegInit();
+       cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
 
        sdram_initialize(1, memctrl);
 
@@ -98,4 +91,3 @@ void main(unsigned long bist)
        void done_cache_as_ram_main(void);
        done_cache_as_ram_main();
 }
-