this should get the VIA VT8454c in shape with Kconfig

[coreboot.git] / src / mainboard / digitallogic / msm800sev / Config.lb

diff --git a/src/mainboard/digitallogic/msm800sev/Config.lb b/src/mainboard/digitallogic/msm800sev/Config.lb
index eceee5bf49e6b533f06d9995d239c5517558dc07..5965cc1d0a2835a4dc49eb34a3c45c3d720eb69b 100644 (file)
--- a/src/mainboard/digitallogic/msm800sev/Config.lb
+++ b/src/mainboard/digitallogic/msm800sev/Config.lb
@@ -1,36 +1,6 @@
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
-       default ROM_SECTION_SIZE   = FALLBACK_SIZE
-       default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
-       default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
-       default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
+include /config/nofailovercalculation.lb
 
 ##
 ## Set all of the defaults for an x86 architecture
@@ -44,21 +14,17 @@ arch i386 end
 
 driver mainboard.o
 
-if HAVE_PIRQ_TABLE
+if CONFIG_GENERATE_PIRQ_TABLE
        object irq_tables.o
 end
 
-if USE_DCACHE_RAM
        #compile cache_as_ram.c to auto.inc
        makerule ./cache_as_ram_auto.inc
-                       depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-                       action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
-                       action "perl -e 's/.rodata/.rom.data/g' -pi $@"
-                       action "perl -e 's/.text/.section .rom.text/g' -pi $@"
+                       depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+                       action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
+                       action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
+                       action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
        end
-end
-
-
 
 ##
 ## Build our 16 bit and 32 bit coreboot entry code
@@ -71,7 +37,7 @@ ldscript /cpu/x86/32bit/entry32.lds
 ##
 ## Build our reset vector (This is where coreboot is entered)
 ##
-if USE_FALLBACK_IMAGE 
+if CONFIG_USE_FALLBACK_IMAGE 
        mainboardinit cpu/x86/16bit/reset16.inc 
        ldscript /cpu/x86/16bit/reset16.lds 
 else
@@ -93,7 +59,7 @@ ldscript /arch/i386/lib/id.lds
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
        ldscript /arch/i386/lib/failover.lds 
 #      mainboardinit ./failover.inc
 end
@@ -105,12 +71,10 @@ end
 ##
 ## Setup RAM
 ##
-mainboardinit cpu/x86/fpu/enable_fpu.inc
+mainboardinit cpu/x86/fpu_enable.inc
 
-if USE_DCACHE_RAM
        mainboardinit cpu/amd/model_lx/cache_as_ram.inc
        mainboardinit ./cache_as_ram_auto.inc
-end
 
 ##
 ## Include the secondary Configuration files