Move "select CACHE_AS_RAM" lines from boards into CPU socket.

[coreboot.git] / src / mainboard / digitallogic / adl855pc / Kconfig

diff --git a/src/mainboard/digitallogic/adl855pc/Kconfig b/src/mainboard/digitallogic/adl855pc/Kconfig
index ccc19c29462cb0a77eba808e24329018a188c334..ec5acb1c0c03f9f5198fa15556dc5f6155595050 100644 (file)
--- a/src/mainboard/digitallogic/adl855pc/Kconfig
+++ b/src/mainboard/digitallogic/adl855pc/Kconfig
@@ -1,25 +1,36 @@
-config BOARD_DIGITALLOGIC_ADL855PC
-       bool "ADL855PC"
+if BOARD_DIGITALLOGIC_ADL855PC
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+       def_bool y
        select ARCH_X86
        select CPU_INTEL_SOCKET_MPGA479M
-       select NORTHBRIDGE_INTEL_I855PM
-       select SOUTHBRIDGE_INTEL_I82801DBM
+       select NORTHBRIDGE_INTEL_I855
+       select SOUTHBRIDGE_INTEL_I82801DX
        select SUPERIO_WINBOND_W83627HF
+       select HAVE_OPTION_TABLE
        select HAVE_PIRQ_TABLE
-       select UDELAY_TSC
+       select HAVE_HARD_RESET
        select BOARD_ROMSIZE_KB_1024
+       select TINY_BOOTBLOCK
 
 config MAINBOARD_DIR
        string
        default digitallogic/adl855pc
-       depends on BOARD_DIGITALLOGIC_ADL855PC
 
 config MAINBOARD_PART_NUMBER
        string
-       default "ADL855PC"
-       depends on BOARD_DIGITALLOGIC_ADL855PC
+       default "smartModule855"
+
+config DCACHE_RAM_BASE
+       hex
+       default 0xffdf8000
+
+config DCACHE_RAM_SIZE
+       hex
+       default 0x8000
 
 config IRQ_SLOT_COUNT
        int
        default 5
-       depends on BOARD_DIGITALLOGIC_ADL855PC
+
+endif # BOARD_DIGITALLOGIC_ADL855PC