#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
#include <console/console.h>
#include "lib/ramtest.c"
#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
#include "s1850_fixups.c"
#include "northbridge/intel/e7520/memory_initialized.c"
#include "cpu/x86/bist.h"
-
-#define SIO_GPIO_BASE 0x680
-#define SIO_XBUS_BASE 0x4880
+#include <spd.h>
#define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, PC8374_SP1)
0 )
#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
-#define RECVENA_CONFIG 0x0808090a
-#define RECVENB_CONFIG 0x0808090a
-
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
-/* this is very highly mainboard dependent, related to wiring */
-/* from factory BIOS via lspci */
-#define DIMM_MAP_LOGICAL 0x2841
#include "northbridge/intel/e7520/raminit.c"
#include "lib/generic_sdram.c"
u16 w;
u32 l;
int do_reset;
- /*
- *
- *
- */
+
static const struct mem_controller mch[] = {
{
.node_id = 0,
*/
/* the wiring on this part is really messed up */
/* this is my best guess so far */
- .channel0 = {(0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, (0xa<<3)|3, },
- .channel1 = {(0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, (0xa<<3)|7, },
+ .channel0 = {DIMM0, DIMM1, DIMM2, DIMM3, },
+ .channel1 = {DIMM4, DIMM5, DIMM6, DIMM7, },
}
};
#if 0
ram_check(0x00000000, 0x02000000);
#endif
-
-#if 0
- while(1) {
- hlt();
- }
-#endif
}
-