#include "s1850_fixups.c"
#include "northbridge/intel/e7520/memory_initialized.c"
#include "cpu/x86/bist.h"
+#include <spd.h>
#define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, PC8374_SP1)
while((inb(ipmicsr) & (1<<OBF)) == 0)
;
}
+
/* quite possibly the stupidest interface ever designed. */
static inline void first_cmd_byte(unsigned char byte)
{
u16 w;
u32 l;
int do_reset;
- /*
- *
- *
- */
+
static const struct mem_controller mch[] = {
{
.node_id = 0,
- /*
- .f0 = PCI_DEV(0, 0x00, 0),
- .f1 = PCI_DEV(0, 0x00, 1),
- .f2 = PCI_DEV(0, 0x00, 2),
- .f3 = PCI_DEV(0, 0x00, 3),
- */
/* the wiring on this part is really messed up */
/* this is my best guess so far */
- .channel0 = {(0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, (0xa<<3)|3, },
- .channel1 = {(0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, (0xa<<3)|7, },
+ .channel0 = {DIMM0, DIMM1, DIMM2, DIMM3, },
+ .channel1 = {DIMM4, DIMM5, DIMM6, DIMM7, },
}
};
if (bist == 0) {
/* Skip this if there was a built in self test failure */
early_mtrr_init();
- if (memory_initialized()) {
+ if (memory_initialized())
skip_romstage();
- }
}
/* Setup the console */
mainboard_set_ich5();
#if 0
// dump_spd_registers(&cpu[0]);
int i;
- for(i = 0; i < 1; i++) {
+ for(i = 0; i < 1; i++)
dump_spd_registers();
- }
#endif
#if 1
show_dram_slots();
#if 0
ram_check(0x00000000, 0x02000000);
#endif
-
-#if 0
- while(1) {
- hlt();
- }
-#endif
}
-