Broadcom BCM5785: Add TINY_BOOTBLOCK support.

[coreboot.git] / src / mainboard / broadcom / blast / romstage.c

diff --git a/src/mainboard/broadcom/blast/romstage.c b/src/mainboard/broadcom/blast/romstage.c
index 447f04d3f0195a222133bf613d072d979ccdf9d7..e3791a79bfefa71306d22991607582b4f063c35a 100644 (file)
--- a/src/mainboard/broadcom/blast/romstage.c
+++ b/src/mainboard/broadcom/blast/romstage.c
@@ -1,8 +1,3 @@
-
-#if CONFIG_LOGICAL_CPUS==1
-#define SET_NB_CFG_54 1
-#endif
-
 #include <stdint.h>
 #include <string.h>
 #include <device/pci_def.h>
@@ -12,37 +7,26 @@
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
-#include "southbridge/broadcom/bcm5785/bcm5785_enable_rom.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/nsc/pc87417/pc87417_early_serial.c"
-
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
-
 #include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1)
 #define RTC_DEV PNP_DEV(0x2e, PC87417_RTC)
 
-#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
-
-static void memreset_setup(void)
-{
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
+static void memreset_setup(void) { }
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
 
 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 {
@@ -70,27 +54,16 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdk8/raminit.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "lib/generic_sdram.c"
-
- /* tyan does not want the default */
 #include "resourcemap.c"
-
 #include "cpu/amd/dualcore/dualcore.c"
-
-#define RC0 (6<<8)
-#define RC1 (7<<8)
-
-#define DIMM0 0x50
-#define DIMM1 0x51
-#define DIMM2 0x52
-#define DIMM3 0x53
-
-
+#include <spd.h>
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/model_fxx/init_cpus.c"
-
 #include "northbridge/amd/amdk8/early_ht.c"
 
+#define RC0 (6<<8)
+#define RC1 (7<<8)
+
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
        static const uint16_t spd_addr[] = {
@@ -101,36 +74,22 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        };
 
         int needs_reset;
-       unsigned bsp_apicid = 0;
-
+       unsigned bsp_apicid = 0, nodes;
         struct mem_controller ctrl[8];
-        unsigned nodes;
 
         if (!cpu_init_detectedx && boot_cpu()) {
                /* Nothing special needs to be done to find bus 0 */
                /* Allow the HT devices to be found */
-
                enumerate_ht_chain();
-
-               bcm5785_enable_rom();
-
                bcm5785_enable_lpc();
-
-               //enable RTC
-               pc87417_enable_dev(RTC_DEV);
+               pc87417_enable_dev(RTC_DEV); /* Enable RTC */
         }
 
-        if (bist == 0) {
+        if (bist == 0)
                bsp_apicid = init_cpus(cpu_init_detectedx);
-        }
-//     post_code(0x32);
 
        pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-//     post_code(0x33);
-
         uart_init();
-//     post_code(0x34);
-
         console_init();
 
        /* Halt if there was a built in self test failure */
@@ -187,13 +146,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 #if 0
         print_pci_devices();
-#endif
-
-#if 0
        dump_pci_devices();
 #endif
 
        post_cache_as_ram();
-
 }
-