Factor out common mptable code to mptable_init().

[coreboot.git] / src / mainboard / broadcom / blast / mptable.c

diff --git a/src/mainboard/broadcom/blast/mptable.c b/src/mainboard/broadcom/blast/mptable.c
index 44bf7f204594c196590d2ceef21e257cf3cffa2a..97bce49ba619c9bd1ed40f969858a8264788e7bb 100644 (file)
--- a/src/mainboard/broadcom/blast/mptable.c
+++ b/src/mainboard/broadcom/blast/mptable.c
@@ -7,7 +7,6 @@
 #if CONFIG_LOGICAL_CPUS==1
 #include <cpu/amd/multicore.h>
 #endif
-
 #include <cpu/amd/amdk8_sysconf.h>
 
 extern  unsigned char bus_isa;
@@ -19,34 +18,15 @@ extern  unsigned apicid_bcm5785[3];
 
 extern  unsigned sbdn2;
 
-
-
 static void *smp_write_config_table(void *v)
 {
-        static const char sig[4] = "PCMP";
-        static const char oem[8] = "BROADCOM";
-        static const char productid[12] = "BLAST       ";
         struct mp_config_table *mc;
-
         unsigned char bus_num;
        int i;
 
         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-        memset(mc, 0, sizeof(*mc));
-
-        memcpy(mc->mpc_signature, sig, sizeof(sig));
-        mc->mpc_length = sizeof(*mc); /* initially just the header */
-        mc->mpc_spec = 0x04;
-        mc->mpc_checksum = 0; /* not yet computed */
-        memcpy(mc->mpc_oem, oem, sizeof(oem));
-        memcpy(mc->mpc_productid, productid, sizeof(productid));
-        mc->mpc_oemptr = 0;
-        mc->mpc_oemsize = 0;
-        mc->mpc_entry_count = 0; /* No entries yet... */
-        mc->mpc_lapic = LAPIC_ADDR;
-        mc->mpe_length = 0;
-        mc->mpe_checksum = 0;
-        mc->reserved = 0;
+
+       mptable_init(mc, "BLAST       ", LAPIC_ADDR);
 
         smp_write_processors(mc);
 
@@ -62,7 +42,6 @@ static void *smp_write_config_table(void *v)
 /*I/O APICs:   APIC ID Version State           Address*/
         {
                 device_t dev = 0;
-               int i;
                struct resource *res;
                for(i=0; i<3; i++) {
                        dev = dev_find_device(0x1166, 0x0235, dev);
@@ -73,24 +52,12 @@ static void *smp_write_config_table(void *v)
                                }
                        }
                }
-               
+
        }
-       
-/*I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
-       smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_bcm5785[0], 0x0);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x1, apicid_bcm5785[0], 0x1); 
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x0, apicid_bcm5785[0], 0x2);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x3, apicid_bcm5785[0], 0x3);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x4, apicid_bcm5785[0], 0x4);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x5, apicid_bcm5785[0], 0x5);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x6, apicid_bcm5785[0], 0x6);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x7, apicid_bcm5785[0], 0x7);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x8, apicid_bcm5785[0], 0x8);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x9, apicid_bcm5785[0], 0x9);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xc, apicid_bcm5785[0], 0xc);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xd, apicid_bcm5785[0], 0xd);
-
-//IDE  
+
+       mptable_add_isa_interrupts(mc, bus_isa, apicid_bcm5785[0], 0);
+
+//IDE
        outb(0x02, 0xc00); outb(0x0e, 0xc01);
 
        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_bcm5785_0, ((1+sysconf.sbdn)<<2)|1, apicid_bcm5785[0], 0xe); // IDE
@@ -98,14 +65,14 @@ static void *smp_write_config_table(void *v)
 //SATA
        outb(0x07, 0xc00); outb(0x0f, 0xc01);
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_1, (0x0e<<2)|0, apicid_bcm5785[0], 0xf);
-       
+
 //USB
        outb(0x01, 0xc00); outb(0x0a, 0xc01);
         for(i=0;i<3;i++) {
                 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, ((2+sysconf.sbdn)<<2)|i, apicid_bcm5785[0], 0xa); //
         }
 
-       
+
 
         /* enable int */
         /* why here? must get the BAR and PCI command bit 1 set before enable it ....*/
@@ -128,13 +95,13 @@ static void *smp_write_config_table(void *v)
         }
 
 
-//pci slot (on bcm5785)  
+//pci slot (on bcm5785)
         for(i=0;i<4;i++) {
                 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, (4<<2)|i, apicid_bcm5785[1], i%2); //
         }
 
 
-//onboard ati 
+//onboard ati
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, (5<<2)|0, apicid_bcm5785[1], 0x1);
 
 //PCI-X on bcm5780
@@ -158,7 +125,7 @@ static void *smp_write_config_table(void *v)
         }
 
 
-// Second PCI-E x8 
+// Second PCI-E x8
         for(i=0;i<4;i++) {
                 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[3], (0<<2)|i, apicid_bcm5785[1], 0xc); //
         }