Remove various .c #includes from Intel 440BX/82371EB boards.

[coreboot.git] / src / mainboard / asus / p3b-f / romstage.c

diff --git a/src/mainboard/asus/p3b-f/romstage.c b/src/mainboard/asus/p3b-f/romstage.c
index 5da8dbf5ca1957110e30413be857ed3633117a0d..04fa6a73c354687e4995e37dad13280da92e6b41 100644 (file)
--- a/src/mainboard/asus/p3b-f/romstage.c
+++ b/src/mainboard/asus/p3b-f/romstage.c
@@ -25,50 +25,76 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <stdlib.h>
-#include "pc80/serial.c"
-#include "console/console.c"
-#include "lib/ramtest.c"
-#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
-#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
+#include <console/console.h>
+#include "southbridge/intel/i82371eb/i82371eb.h"
 #include "northbridge/intel/i440bx/raminit.h"
-#include "lib/debug.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 /* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */
 #include "superio/winbond/w83977tf/w83977tf_early_serial.c"
+#include <lib.h>
+
+void enable_pm(void);
+void enable_smbus(void);
+int smbus_read_byte(u8 device, u8 address);
 
 /* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
 
-static inline int spd_read_byte(unsigned int device, unsigned int address)
+int spd_read_byte(unsigned int device, unsigned int address)
 {
        return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/i440bx/raminit.c"
-#include "northbridge/intel/i440bx/debug.c"
+/*
+ * ASUS P3B-F specific SPD enable magic.
+ *
+ * Setting the byte at offset 0x37 in the PM I/O space to 0x6f will make the
+ * board DIMMs accessible at SMBus/SPD offsets 0x50-0x53. Per default the SPD
+ * offsets 0x50-0x53 are _not_ readable (all SPD reads will return 0xff) which
+ * will make RAM init fail.
+ *
+ * Tested values for PM I/O offset 0x37:
+ * 0x67: 11 00 111: Only SMBus/I2C offsets 0x48/0x49/0x2d accessible
+ * 0x6f: 11 01 111: Only SMBus/I2C offsets 0x50-0x53 (SPD) accessible
+ * 0x77: 11 10 111: Only SMBus/I2C offset 0x69 accessible
+ *
+ * PM I/O space offset 0x37 is GPOREG[31:24], i.e. it controls the GPIOs
+ * 24-30 of the PIIX4E (bit 31 is reserved). Thus, GPIOs 27 and 28
+ * control which SMBus/I2C offsets can be accessed.
+ */
+static void enable_spd(void)
+{
+       outb(0x6f, PM_IO_BASE + 0x37);
+}
 
-static void main(unsigned long bist)
+/*
+ * Disable SPD access after RAM init to allow access to SMBus/I2C offsets
+ * 0x48/0x49/0x2d, which is required e.g. by lm-sensors.
+ */
+static void disable_spd(void)
 {
-       if (bist == 0)
-               early_mtrr_init();
+       outb(0x67, PM_IO_BASE + 0x37);
+}
 
+void main(unsigned long bist)
+{
        /* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */
        w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
        uart_init();
        console_init();
        report_bist_failure(bist);
 
-       /* Enable access to the full ROM chip, needed very early by CBFS. */
-       i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge is 00:04.0. */
-
        enable_smbus();
-       /* dump_spd_registers(); */
+       enable_pm();
+
+       enable_spd();
+
+       dump_spd_registers();
        sdram_set_registers();
        sdram_set_spd_registers();
        sdram_enable();
-       /* ram_check(0, 640 * 1024); */
-}
 
+       disable_spd();
+}