#include <console/console.h>
#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
-void *smp_write_config_table(void *v)
+static void *smp_write_config_table(void *v)
{
- static const char sig[4] = "PCMP";
- static const char oem[8] = "COREBOOT";
- static const char productid[12] = "ASUS P2B-D ";
+ int ioapic_id, ioapic_ver, isa_bus;
struct mp_config_table *mc;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
- memset(mc, 0, sizeof(*mc));
- memcpy(mc->mpc_signature, sig, sizeof(sig));
- mc->mpc_length = sizeof(*mc); /* initially just the header */
- mc->mpc_spec = 0x04;
- mc->mpc_checksum = 0; /* not yet computed */
- memcpy(mc->mpc_oem, oem, sizeof(oem));
- memcpy(mc->mpc_productid, productid, sizeof(productid));
- mc->mpc_oemptr = 0;
- mc->mpc_oemsize = 0;
- mc->mpc_entry_count = 0; /* No entries yet... */
- mc->mpc_lapic = LAPIC_ADDR;
- mc->mpe_length = 0;
- mc->mpe_checksum = 0;
- mc->reserved = 0;
+ mptable_init(mc, "P2B-D ", LAPIC_ADDR);
smp_write_processors(mc);
- /* Bus: Bus ID Type */
- smp_write_bus(mc, 0, "PCI ");
- smp_write_bus(mc, 1, "PCI ");
- smp_write_bus(mc, 2, "ISA ");
+ mptable_write_buses(mc, NULL, &isa_bus);
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, 2, 0x20, 0xfec00000);
- {
- device_t dev;
- struct resource *res;
- dev = dev_find_slot(1, PCI_DEVFN(0x1e, 0));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res)
- smp_write_ioapic(mc, 3, 0x20, res->base);
- }
- dev = dev_find_slot(1, PCI_DEVFN(0x1c, 0));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res)
- smp_write_ioapic(mc, 4, 0x20, res->base);
- }
- dev = dev_find_slot(4, PCI_DEVFN(0x1e, 0));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res)
- smp_write_ioapic(mc, 5, 0x20, res->base);
- }
- dev = dev_find_slot(4, PCI_DEVFN(0x1c, 0));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res)
- smp_write_ioapic(mc, 8, 0x20, res->base);
- }
- }
+ ioapic_id = 2;
+ ioapic_ver = 0x11; /* External Intel 82093AA IOAPIC. */
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- smp_write_intsrc(mc, mp_ExtINT,
- MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x2,
- 0x0, 0x2, 0x0);
- smp_write_intsrc(mc, mp_INT,
- MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x2,
- 0x1, 0x2, 0x1);
- smp_write_intsrc(mc, mp_INT,
- MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x2,
- 0x0, 0x2, 0x2);
- smp_write_intsrc(mc, mp_INT,
- MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x2,
- 0x3, 0x2, 0x3);
- smp_write_intsrc(mc, mp_INT,
- MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x2,
- 0x4, 0x2, 0x4);
- smp_write_intsrc(mc, mp_INT,
- MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x2,
- 0x5, 0x2, 0x5);
- smp_write_intsrc(mc, mp_INT,
- MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x2,
- 0x6, 0x2, 0x6);
- smp_write_intsrc(mc, mp_INT,
- MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x2,
- 0x7, 0x2, 0x7);
- smp_write_intsrc(mc, mp_INT,
- MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x2,
- 0x8, 0x2, 0x8);
- smp_write_intsrc(mc, mp_INT,
- MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x2,
- 0x9, 0x2, 0x9);
- smp_write_intsrc(mc, mp_INT,
- MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x2,
- 0xc, 0x2, 0xc);
- smp_write_intsrc(mc, mp_INT,
- MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x2,
- 0xe, 0x2, 0xe);
- smp_write_intsrc(mc, mp_INT,
- MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x2,
- 0xf, 0x2, 0xf);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
- 0x2, 0xb, 0x2, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
- 0x2, 0xa, 0x2, 0x13);
+ /* Legacy Interrupts */
+ mptable_add_isa_interrupts(mc, isa_bus, ioapic_id, 0);
- /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- smp_write_intsrc(mc, mp_ExtINT,
- MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 0x2, 0x0,
- MP_APIC_ALL, 0x0);
- smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
- 0x2, 0x0, MP_APIC_ALL, 0x1);
+ /* I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x13, ioapic_id, 0x13); /* UHCI */
- /* There is no extension information... */
+ /* Local Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */
+ smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, isa_bus, 0x0, MP_APIC_ALL, 0x0);
+ smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, isa_bus, 0x0, MP_APIC_ALL, 0x1);
- /* Compute the checksums */
+ /* Compute the checksums. */
mc->mpe_checksum =
smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
projects / coreboot.git / blobdiff