Enable mahogany_fam10 and Kino family 10h to run the SB HT link at the expected HT3...

[coreboot.git] / src / mainboard / asus / m4a785-m / romstage.c

diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
index f524a889d3a413aa46c5a46606c2b1f0aba6f73e..4c9543beb1e718fcb427f65556402292b753bbe2 100644 (file)
--- a/src/mainboard/asus/m4a785-m/romstage.c
+++ b/src/mainboard/asus/m4a785-m/romstage.c
@@ -38,61 +38,47 @@
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #include <lib.h>
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"
-
 #include <console/loglevel.h>
 #include "cpu/x86/bist.h"
-
-static int smbus_read_byte(u32 device, u32 address);
-
-#include "superio/ite/it8712f/it8712f_early_serial.c"
+#include "superio/ite/it8712f/early_serial.c"
 #include <usbdebug.h>
-
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
-
-#include "southbridge/amd/rs780/rs780_early_setup.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
+#include "southbridge/amd/rs780/early_setup.c"
+#include "southbridge/amd/sb700/early_setup.c"
 #include "northbridge/amd/amdfam10/debug.c"
 
-static void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
 
 static int spd_read_byte(u32 device, u32 address)
 {
-       int result;
-       result = smbus_read_byte(device, address);
-       return result;
+       return smbus_read_byte(device, address);
 }
 
 #include "northbridge/amd/amdfam10/amdfam10.h"
-
 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
-#include "northbridge/amd/amdfam10/amdfam10_pci.c"
-
+#include "northbridge/amd/amdfam10/pci.c"
 #include "resourcemap.c"
 #include "cpu/amd/quadcore/quadcore.c"
-
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/microcode/microcode.c"
+
+#if CONFIG_UPDATE_CPU_MICROCODE
 #include "cpu/amd/model_10xxx/update_microcode.c"
-#include "cpu/amd/model_10xxx/init_cpus.c"
+#endif
 
+#include "cpu/amd/model_10xxx/init_cpus.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
 #include <spd.h>
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-
        struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
        static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
-       u32 bsp_apicid = 0;
-       u32 val;
+       u32 bsp_apicid = 0, val;
        msr_t msr;
 
        if (!cpu_init_detectedx && boot_cpu()) {
@@ -101,7 +87,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
                /* mov bsp to bus 0xff when > 8 nodes */
                set_bsp_node_CHtExtNodeCfgEn();
                enumerate_ht_chain();
-
                sb700_pci_port80();
        }
 
@@ -118,7 +103,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        sb700_lpc_init();
 
        it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
-       it8712f_kill_watchdog(); /* disable watchdog, so it does not reset while still booting */
+       it8712f_kill_watchdog();
        uart_init();
 
 #if CONFIG_USBDEBUG
@@ -144,7 +129,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        /* Setup sysinfo defaults */
        set_sysinfo_in_ram(0);
 
+#if CONFIG_UPDATE_CPU_MICROCODE
        update_microcode(val);
+#endif
        post_code(0x33);
 
        cpuSetAMDMSR();
@@ -235,10 +222,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
 */
 
-//     ram_check(0x00200000, 0x00200000 + (640 * 1024));
-//     ram_check(0x40200000, 0x40200000 + (640 * 1024));
-
-
 //     die("After MCT init before CAR disabled.");
 
        rs780_before_pci_init();
@@ -249,3 +232,37 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        post_cache_as_ram();    // BSP switch stack to ram, copy then execute LB.
        post_code(0x43);        // Should never see this post code.
 }
+
+/**
+ * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
+ * Description:
+ *     This routine is called every time a non-coherent chain is processed.
+ *     BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
+ *     swap list. The first part of the list controls the BUID assignment and the
+ *     second part of the list provides the device to device linking.  Device orientation
+ *     can be detected automatically, or explicitly.  See documentation for more details.
+ *
+ *     Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
+ *     based on each device's unit count.
+ *
+ * Parameters:
+ *     @param[in]  u8  node    = The node on which this chain is located
+ *     @param[in]  u8  link    = The link on the host for this chain
+ *     @param[out] u8** list   = supply a pointer to a list
+ *     @param[out] BOOL result = true to use a manual list
+ *                               false to initialize the link automatically
+ */
+BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
+{
+       static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
+       /* If the BUID was adjusted in early_ht we need to do the manual override */
+       if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {
+               printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n");
+               if ((node == 0) && (link == 0)) {       /* BSP SB link */
+                       *List = swaplist;
+                       return 1;
+               }
+       }
+
+       return 0;
+}