Remove old AMD fam10 fixme comment

[coreboot.git] / src / mainboard / asus / m4a78-em / romstage.c

diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c
index 4c9543beb1e718fcb427f65556402292b753bbe2..a96592d20c69fee90e519eb3ddbb1385e90b1650 100644 (file)
--- a/src/mainboard/asus/m4a78-em/romstage.c
+++ b/src/mainboard/asus/m4a78-em/romstage.c
@@ -43,19 +43,19 @@
 #include <console/loglevel.h>
 #include "cpu/x86/bist.h"
 #include "superio/ite/it8712f/early_serial.c"
-#include <usbdebug.h>
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
 #include "southbridge/amd/rs780/early_setup.c"
-#include "southbridge/amd/sb700/early_setup.c"
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
 #include "northbridge/amd/amdfam10/debug.c"
 
 static void activate_spd_rom(const struct mem_controller *ctrl) { }
 
 static int spd_read_byte(u32 device, u32 address)
 {
-       return smbus_read_byte(device, address);
+       return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
 }
 
 #include "northbridge/amd/amdfam10/amdfam10.h"
@@ -87,7 +87,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
                /* mov bsp to bus 0xff when > 8 nodes */
                set_bsp_node_CHtExtNodeCfgEn();
                enumerate_ht_chain();
-               sb700_pci_port80();
+               sb7xx_51xx_pci_port80();
        }
 
        post_code(0x30);
@@ -100,19 +100,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        post_code(0x32);
 
        enable_rs780_dev8();
-       sb700_lpc_init();
+       sb7xx_51xx_lpc_init();
 
        it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
        it8712f_kill_watchdog();
-       uart_init();
-
-#if CONFIG_USBDEBUG
-       sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-       early_usbdebug_init();
-#endif
 
        console_init();
-       printk(BIOS_DEBUG, "\n");
 
 //     dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 
@@ -167,7 +160,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
        /* run _early_setup before soft-reset. */
        rs780_early_setup();
-       sb700_early_setup();
+       sb7xx_51xx_early_setup();
 
  #if CONFIG_SET_FIDVID
        msr = rdmsr(0xc0010071);
@@ -225,10 +218,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 //     die("After MCT init before CAR disabled.");
 
        rs780_before_pci_init();
-       sb700_before_pci_init();
+       sb7xx_51xx_before_pci_init();
 
        post_code(0x42);
-       printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
        post_cache_as_ram();    // BSP switch stack to ram, copy then execute LB.
        post_code(0x43);        // Should never see this post code.
 }