Since some people disapprove of white space cleanups mixed in regular commits

[coreboot.git] / src / mainboard / asus / m2v-mx_se / romstage.c

diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c
index 1ee6ab0a5d0d79206694ded26008b348495bdfdf..ea9870798c08a7d56b6331660e6911baebb8370a 100644 (file)
--- a/src/mainboard/asus/m2v-mx_se/romstage.c
+++ b/src/mainboard/asus/m2v-mx_se/romstage.c
@@ -5,7 +5,7 @@
  * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
  * Copyright (C) 2006 MSI
  * (Written by Bingxun Shi <bingxunshi@gmail.com> for MSI)
- * Copyright (C) 2008 Rudolf Marek <r.marek@assembler.cz> 
+ * Copyright (C) 2008 Rudolf Marek <r.marek@assembler.cz>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -57,23 +57,18 @@ unsigned int get_sbdn(unsigned bus);
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
 #include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
 #define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO)
 
-static void memreset_setup(void)
-{
-}
-
 static void memreset(int controllers, const struct mem_controller *ctrl)
 {
 }
@@ -83,18 +78,21 @@ static inline int spd_read_byte(unsigned device, unsigned address)
        return smbus_read_byte(device, address);
 }
 
-void activate_spd_rom(const struct mem_controller *ctrl)
+static void activate_spd_rom(const struct mem_controller *ctrl)
 {
 }
 
+// defines S3_NVRAM_EARLY:
+#include "southbridge/via/k8t890/k8t890_early_car.c"
+
 #define K8_4RANK_DIMM_SUPPORT 1
 
-#include "southbridge/via/k8t890/k8t890_early_car.c"
 #include "northbridge/amd/amdk8/amdk8.h"
-#include "northbridge/amd/amdk8/raminit_f.c"
-#include "northbridge/amd/amdk8/coherent_ht.c"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
+#include "northbridge/amd/amdk8/coherent_ht.c"
+#include "northbridge/amd/amdk8/raminit_f.c"
 #include "lib/generic_sdram.c"
+
 #include "cpu/amd/dualcore/dualcore.c"
 
 #include "cpu/amd/car/post_cache_as_ram.c"
@@ -144,34 +142,21 @@ unsigned int get_sbdn(unsigned bus)
        return (dev >> 15) & 0x1f;
 }
 
-void sio_init(void)
-{
-
-}
-
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
-       real_main(bist, cpu_init_detectedx);
-}
-
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
        static const uint16_t spd_addr[] = {
+               // Node 0
                (0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
                (0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
-#if CONFIG_MAX_PHYSICAL_CPUS > 1
+               // Node 1
                (0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
                (0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
-#endif
        };
        unsigned bsp_apicid = 0;
        int needs_reset = 0;
        struct sys_info *sysinfo =
            (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 
-       sio_init();
        it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
        it8712f_kill_watchdog();
        it8712f_enable_3vsbsw();
@@ -179,7 +164,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
        console_init();
        enable_rom_decode();
 
-       print_info("now booting... real_main\n");
+       printk(BIOS_INFO, "now booting... \n");
 
        if (bist == 0)
                bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
@@ -190,7 +175,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
        setup_coherent_ht_domain();
        wait_all_core0_started();
 
-       print_info("now booting... Core0 started\n");
+       printk(BIOS_INFO, "now booting... All core 0 started\n");
 
 #if CONFIG_LOGICAL_CPUS==1
        /* It is said that we should start core1 after all core0 launched. */
@@ -211,12 +196,9 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
        vt8237_early_spi_init();
 
        if (needs_reset) {
-               print_debug_hex8(needs_reset);
-
-               print_debug("Xht reset -\n");
+               printk(BIOS_DEBUG, "ht reset -\n");
                soft_reset();
-               print_debug("NO reset\n");
-
+               printk(BIOS_DEBUG, "FAILED!\n");
        }
 
        /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */
@@ -234,7 +216,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
        /* It's the time to set ctrl now. */
        fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
        enable_smbus();
-       memreset_setup();
        sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
        post_cache_as_ram();
 }