Fix all warnings in the tree

[coreboot.git] / src / mainboard / asus / m2v-mx_se / romstage.c

diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c
index 3ece7aa22b92d705dfe8086505dfb7e66b6235dc..cbf8ef570be99f4cc6ecaa86dd31327891d387f1 100644 (file)
--- a/src/mainboard/asus/m2v-mx_se/romstage.c
+++ b/src/mainboard/asus/m2v-mx_se/romstage.c
@@ -5,7 +5,7 @@
  * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
  * Copyright (C) 2006 MSI
  * (Written by Bingxun Shi <bingxunshi@gmail.com> for MSI)
- * Copyright (C) 2008 Rudolf Marek <r.marek@assembler.cz> 
+ * Copyright (C) 2008 Rudolf Marek <r.marek@assembler.cz>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -49,18 +49,14 @@ unsigned int get_sbdn(unsigned bus);
 #include <arch/romcc_io.h>
 #include <cpu/amd/mtrr.h>
 #include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
-#include "northbridge/amd/amdk8/early_ht.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
 #include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
@@ -83,10 +79,11 @@ static void activate_spd_rom(const struct mem_controller *ctrl)
 {
 }
 
-#define K8_4RANK_DIMM_SUPPORT 1
-
+// defines S3_NVRAM_EARLY:
 #include "southbridge/via/k8t890/k8t890_early_car.c"
 
+#define K8_4RANK_DIMM_SUPPORT 1
+
 #include "northbridge/amd/amdk8/amdk8.h"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
@@ -164,7 +161,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        console_init();
        enable_rom_decode();
 
-       print_info("now booting... real_main\n");
+       printk(BIOS_INFO, "now booting... \n");
 
        if (bist == 0)
                bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
@@ -175,7 +172,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        setup_coherent_ht_domain();
        wait_all_core0_started();
 
-       print_info("now booting... Core0 started\n");
+       printk(BIOS_INFO, "now booting... All core 0 started\n");
 
 #if CONFIG_LOGICAL_CPUS==1
        /* It is said that we should start core1 after all core0 launched. */
@@ -196,12 +193,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        vt8237_early_spi_init();
 
        if (needs_reset) {
-               print_debug_hex8(needs_reset);
-
-               print_debug("Xht reset -\n");
+               printk(BIOS_DEBUG, "ht reset -\n");
                soft_reset();
-               print_debug("NO reset\n");
-
+               printk(BIOS_DEBUG, "FAILED!\n");
        }
 
        /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */