Following patch adds support for the ACPI resume on Asus M2V-MX SE. The ACPI

[coreboot.git] / src / mainboard / asus / m2v-mx_se / mainboard.c

diff --git a/src/mainboard/asus/m2v-mx_se/mainboard.c b/src/mainboard/asus/m2v-mx_se/mainboard.c
index 2a5910b3a329974047473fc480ca95ab16aa6956..ce3b66c4b867cfbcdd83bb9253cb1cae0594986b 100644 (file)
--- a/src/mainboard/asus/m2v-mx_se/mainboard.c
+++ b/src/mainboard/asus/m2v-mx_se/mainboard.c
@@ -21,10 +21,28 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
+#include <boot/tables.h>
 #include "chip.h"
 
-#if CONFIG_CHIP_NAME == 1
+/* in arch/i386/boot/tables.c */
+extern uint64_t high_tables_base, high_tables_size;
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+#if HAVE_HIGH_TABLES == 1
+       printk_debug("Adding high table area\n");
+       lb_add_memory_range(mem, LB_MEM_TABLE,
+               high_tables_base, high_tables_size);
+#endif
+#if HAVE_ACPI_RESUME == 1
+       lb_add_memory_range(mem, LB_MEM_RESERVED,
+               _RAMBASE, ((CONFIG_LB_MEM_TOPK<<10) - _RAMBASE));
+       lb_add_memory_range(mem, LB_MEM_RESERVED,
+               DCACHE_RAM_BASE, DCACHE_RAM_SIZE);
+#endif
+       return 0;
+}
+
 struct chip_operations mainboard_ops = {
        CHIP_NAME("ASUS M2V-MX SE Mainboard")
 };
-#endif